Solid-state imaging device

1. An imaging device, comprising:

a first chip including:

a first pixel and a second pixel, the first pixel including a first anode region and a first cathode region, the second pixel including a second anode region and a second cathode region; and

a first wiring layer including:

a first anode electrode;

a first anode via coupled to the first anode electrode and the first anode region; and

a second anode via coupled to the first anode electrode and the second anode region.

2. The imaging device of claim 1 , wherein, in a plan view, the first and second pixels are adjacent to one another, and wherein, in the plan view, the first anode electrode and the first and second anode vias are between the first and second cathode regions.

3. The imaging device of claim 2 , wherein the first chip further comprises:

an insulating material between the first anode region and the second anode region, and wherein, in the plan view, the first anode electrode overlaps portions of the first anode region, the second anode region, and the insulating material.

4. The imaging device of claim 2 , wherein, in the plan view, the first and second anode vias are aligned with one another along a first direction.

5. The imaging device of claim 1 , further comprising:

a second chip bonded to the first chip and including circuitry for processing signals from the first and second pixels.

6. The imaging device of claim 5 , wherein the second chip further comprises a second wiring layer that includes:

a second anode electrode coupled to the first anode electrode;

a first anode wiring;

a third anode via coupled to the second anode electrode and the first anode wiring; and

a fourth anode via coupled to the second anode electrode and the first anode wiring.

7. The imaging device of claim 1 , wherein the first wiring layer further comprises:

a first cathode electrode;

a first cathode via coupled to the first cathode region and the first cathode electrode;

a second cathode electrode; and

a second cathode via coupled to the second cathode region and the second cathode electrode.

8. The imaging device of claim 7 , further comprising:

a second chip bonded to the first chip and including circuitry for processing signals from the first and second pixels, the second chip including a second wiring layer that includes:

a second anode electrode coupled to the first anode electrode;

a first anode wiring;

a third anode via coupled to the second anode electrode and the first anode wiring; and

a fourth anode via coupled to the second anode electrode and the first anode wiring.

9. The imaging device of claim 8 , wherein the second wiring layer further comprises:

a third cathode electrode coupled to the first cathode electrode;

a first cathode wiring;

a third cathode via coupled to the third cathode electrode and the first cathode wiring;

a fourth cathode electrode coupled to the second cathode electrode;

a second cathode wiring; and

a fourth cathode via coupled to the fourth cathode electrode and the second cathode wiring.

10. The imaging device of claim 9 , wherein the second wiring layer further comprises:

a third cathode wiring;

a fifth cathode via coupled to the first cathode wiring and the third cathode wiring;

a fourth cathode wiring; and

a sixth cathode via coupled to the second cathode wiring and the third cathode wiring.

11. The imaging device of claim 1 , wherein the first wiring layer further comprises:

a first cathode electrode;

a first cathode wiring between the first cathode electrode and the first cathode region in a cross-sectional view, wherein the first cathode wiring is coupled to the first cathode electrode; and

a plurality of cathode vias coupled to the first cathode region and the first cathode wiring.

12. The imaging device of claim 11 , wherein, in a plan view, a first cathode via of the plurality of cathode vias is at a center portion of the first cathode region and a remainder of the plurality of cathode vias are at edge portions of the first cathode region.

13. The imaging device of claim 12 , wherein the remainder of the plurality of cathode vias are arranged symmetrically around the first cathode via at the edge portions of the first cathode region.

14. The imaging device of claim 11 , wherein the first wiring layer further comprises:

a first shield wiring that overlaps the first anode region and the second anode region in a plan view.

15. The imaging device of claim 14 , wherein the first shield wiring is coplanar with the first cathode wiring.

16. The imaging device of claim 14 , wherein the first wiring layer further comprises:

a second shield wiring that overlaps the first cathode wiring and the first shield wiring in the plan view.

17. The imaging device of claim 16 , wherein the second shield wiring is coplanar with the first cathode electrode.

18. An imaging device, comprising:

a first chip including:

a first pixel including a first anode region and a first cathode region; and

a first wiring layer including:

a first cathode electrode;

a first cathode wiring between the first cathode electrode and the first cathode region in a cross-sectional view, wherein the first cathode wiring is coupled to the first cathode electrode; and

a plurality of cathode vias coupled to the first cathode region and the first cathode wiring.

19. The imaging device of claim 18 , wherein, in a plan view, a first cathode via of the plurality of cathode vias is at a center portion of the first cathode region and a remainder of the plurality of cathode vias are arranged symmetrically around the first cathode via at edge portions of the first cathode region.

20. An electronic device, comprising:

an imaging device including a first chip, the first chip including:

a first pixel and a second pixel, the first pixel including a first anode region and a first cathode region, the second pixel including a second anode region and a second cathode region; and

a first wiring layer including:

a first anode electrode;

a first anode via coupled to the first anode electrode and the first anode region; and

a second anode via coupled to the first anode electrode and the second anode region.