Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors

1. A method of forming a semiconductor device comprising:

forming a semiconductor fin structure having sidewalls with {100} crystalline planes that is present atop a supporting substrate;

forming a first source/drain region on the supporting substrate at a base of the fin structure;

forming a gate structure on a vertically orientated channel region portion of the fin structure over the first source/drain region;

epitaxially growing a second source/drain region in a lateral direction from the sidewalls of the semiconductor fin structure having sidewalls with {100} crystalline planes, wherein the second source/drain regions have substantially planar sidewalls; and

forming a metal wrap around electrode on an upper surface and the substantially planar sidewalls of the second source/drain region.

2. The method of claim 1 , wherein said forming the semiconductor fin structure having sidewalls with {100} crystalline planes that is present atop the supporting substrate comprises:

rotating a {100} substrate that is comprised of a silicon containing material by 45 degrees; and

etching the substrate that is composed of the {100} substrate that is comprised of the silicon containing material following said rotating to provide said fin structure having sidewalls with {100} crystalline planes.

3. The method of claim 1 , wherein said forming the metal wrap around electrode on the upper surface and the substantially planar sidewalls of the second source/drain region comprises:

forming a sacrificial silicon and germanium containing conformal layer on the upper surface and substantially planar sidewalls of the second source/drain region;

forming a germanium and oxygen containing layer on the sacrificial silicon and germanium containing conformal layer;

converting the germanium and oxygen containing layer to a silicon and oxygen containing layer by thermal anneal in a nitrogen gas (N2) atmosphere;

forming an encapsulating layer over on the silicon and oxygen containing layer and covering the second source/drain region;

forming a via opening through the encapsulating layer to expose a portion of the silicon and oxygen containing layer;

removing the silicon and oxygen containing layer with an etch that is selective to the second source/drain region and the encapsulating layer to form a passageway opening for the metal wrap around electrode; and

filling the passageway opening with a metal to provide the metal wrap around electrode.

4. The method of claim 1 , wherein the second source/drain region has a silicon and germanium containing surface, wherein said forming the metal wrap around electrode on the upper surface and the substantially planar sidewalls of the second source/drain region comprises:

forming a germanium and oxygen containing layer on the upper surface and substantially planar sidewalls of the second source/drain region;

converting the germanium and oxygen containing layer to a silicon and oxygen containing layer by thermal anneal in a nitrogen gas (N2) atmosphere;

forming an encapsulating layer over on the silicon and oxygen containing layer and covering the second source/drain region;

forming a via opening through the encapsulating layer to expose a portion of the silicon and oxygen containing layer;

removing the silicon and oxygen containing layer with an etch that is selective to the second source/drain region and the encapsulating layer to form a passageway opening for the metal wrap around electrode; and

filling the passageway opening with a metal to provide the metal wrap around electrode.

5. The method of claim 4 , wherein said filling the passageway opening with the metal to provide the metal wrap around electrode comprises chemical vapor deposition (CVD) using a two-stage deposition process that includes a first deposition of titanium and a second deposition or cobalt or tungsten.

6. The method of claim 4 , further comprising forming an air gap adjacent to the substantially planar sidewalls of the second source/drain region.

7. The method of claim 6 , further comprising an isolating stack between the gate structure and a bottom surface of the second source/drain region, the isolation stack including an etch stop liner of silicon boron carbon nitride (SiBCN) that is present on the gate structure, and a nitride containing dielectric present on the etch stop liner.

8. The method of claim 7 , wherein the encapsulating dielectric is composed of amorphous silicon.

9. The method of claim 8 , wherein the forming of the air gap comprises:

removing the encapsulating dielectric and the nitride containing dielectric of the isolation stack selectively to the etch stop liner providing a first opening type between a bottom surface of the second source/drain region and the gate structure, and a second opening type adjacent to the substantially planar sidewall of the second source/drain region; and

depositing a dielectric material that pinches off in the first and second type openings to form said air gaps.

10. A method of forming a semiconductor device comprising:

forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate;

epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure of the at least two semiconductor fin structures having the sidewalls with the {100} crystalline planes, wherein the source/drain regions have substantially planar sidewalls and are present at an end of each of the fin structures opposite an end that is in contact with the supporting substrate;

forming a metal wrap around electrode on an upper surface and the substantially planar sidewalls of the source/drain regions; and

forming air gaps between the source/drain regions of the at least two semiconductor fin structures.

11. The method of claim 10 , wherein said forming the at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop the supporting substrate comprises:

rotating a {100} substrate that is comprised of a silicon containing material by 45 degrees; and

etching the substrate that is composed of the {100} substrate that is comprised of the silicon containing material following said rotating to provide said fin structure having sidewalls with {100} crystalline planes.

12. The method of claim 11 , wherein said forming the metal wrap around electrode on the upper surface and the substantially planar sidewalls of the source/drain regions comprises:

forming a sacrificial silicon and germanium containing conformal layer on the upper surface and substantially planar sidewalls of the source/drain regions;

forming a germanium and oxygen containing layer on the sacrificial silicon and germanium containing conformal layer;

converting the germanium and oxygen containing layer to a silicon and oxygen containing layer by thermal anneal in a nitrogen gas (N2) atmosphere;

forming an encapsulating layer over on the silicon and oxygen containing layer and covering the source/drain region;

forming a via opening through the encapsulating layer to expose a portion of the silicon and oxygen containing layer;

removing the silicon and oxygen containing layer with an etch that is selective to the source/drain regions and the encapsulating layer to form a passageway opening for the metal wrap around electrode; and

filling the passageway opening with a metal to provide the metal wrap around electrodes.

13. The method of claim 11 , wherein the source/drain regions have a silicon and germanium containing surface, wherein said forming the metal wrap around electrode on the upper surface and the substantially planar sidewalls of the source/drain regions comprises:

forming a germanium and oxygen containing layer on the upper surface and substantially planar sidewalls of the source/drain region;

converting the germanium and oxygen containing layer to a silicon and oxygen containing layer by thermal anneal in a nitrogen gas (N 2 ) atmosphere;

forming an encapsulating layer over on the silicon and oxygen containing layer and covering the source/drain region;

forming a via opening through the encapsulating layer to expose a portion of the silicon and oxygen containing layer;

removing the silicon and oxygen containing layer with an etch that is selective to the source/drain region and the encapsulating layer to form a passageway opening for the metal wrap around electrode; and

filling the passageway opening with a metal to provide the metal wrap around electrode.

14. The method of claim 13 , wherein the forming of the air gap comprises:

removing the encapsulating dielectric to provide a first opening type between a bottom surface of the source/drain region and a gate structure, and a second opening type adjacent to the substantially planar sidewall of the source/drain region between the at least two semiconductor fin structures; and

depositing a dielectric material that pinches off in the first and second type openings to form said air gaps.