Field-effect transistor comprising germanium and manufacturing method thereof
The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiO x (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.
1. A field-effect transistor (FET), comprising:
an active region comprising germanium (Ge); and
a gate stack formed on the active region, the gate stack comprising:
a passivation layer formed on the active region and comprising a Si layer having a thickness between 1 and 8 monolayers,
an interfacial dielectric layer formed on the passivation layer and comprising SiO x , wherein x is greater than 0,
an Si/SiO x interface between the passivation layer and the interfacial dielectric layer,
a dielectric capping layer separately deposited on the interfacial dielectric layer and comprising an interface dipole-forming material,
a high-k dielectric layer formed on the dielectric capping layer, and
a gate electrode layer formed on the high-k dielectric layer.
2. The FET according to claim 1 , wherein the dielectric capping layer is in physical contact with the interfacial dielectric layer and the high-k dielectric layer.
3. The FET according to claim 1 , wherein the interface dipole-forming material comprises a rare earth element.
4. The FET according to claim 3 , wherein the rare earth element is selected from the group consisting of lanthanum (La), yttrium (Y), magnesium (Mg), erbium (Er), dysprosium (Dy) and gadolinium (Gd).
5. The FET according to claim 1 , wherein the dielectric capping layer is a transition metal oxide layer or a transition metal silicate layer.
6. The FET according to claim 5 , wherein the dielectric capping layer comprises La x O z , where x and z are each greater than 0.
7. The FET according to claim 5 , wherein the dielectric capping layer comprises La x Si y O z , where x, y and z are each greater than 0.
8. The FET according to claim 1 , wherein the thickness of the passivation layer is between 1 and 5 monolayers.
9. The FET according claim 1 , wherein the high-k dielectric layer is formed of any of HfO x , HfSiO x , HfSiON, LaO x , ZrO x , ZrSiO x , TaO x , AlO x or any combination thereof.
10. The FET according to claim 1 , wherein the gate electrode layer comprises a metal selected from the group consisting of TiN, TiAl, TaN, TaC, TiC, Ti, Ta, Mo, Ru and W.
11. The FET according to claim 1 , wherein the interfacial dielectric layer comprises SiO x or SiO 2 , and the dielectric capping layer comprises a lanthanum oxide or a lanthanum silicate.
12. The FET according to claim 1 , wherein the FET is a FinFET or a gate all-around (GAA) FET.
13. A method of manufacturing a field-effect transistor (FET), the method comprising:
providing an active region comprising germanium (Ge);
forming a gate stack on the active region, comprising:
forming on the active region a passivation layer comprising a Si layer having a thickness between 1 and 8 monolayers,
forming on the passivation layer an interfacial dielectric layer comprising SiO x , wherein x is greater than 0, whereby an Si/SiO x interface is formed between the passivation layer and the interfacial dielectric layer,
separately depositing on the interfacial dielectric layer a dielectric capping layer comprising an interface dipole-forming material,
forming on the dielectric capping layer a high-k dielectric layer, and
forming on the high-k dielectric layer a gate electrode layer.
14. The method according to claim 13 , wherein separately depositing the dielectric capping layer comprises depositing by physical vapor deposition (PVD).
15. The method according to claim 13 , wherein separately depositing the dielectric capping layer comprises depositing by atomic layer deposition (ALD).
16. The method according to claim 13 , wherein forming the passivation layer comprises depositing the passivation layer having a thickness of 1 to 5 monolayers.
17. The method according to claim 16 , wherein forming the interfacial dielectric layer comprises partially oxidizing the passivation layer.
18. The method according to claim 17 , wherein partially oxidizing the passivation layer comprises reducing the thickness of the passivation layer by more than 50%.
19. The method according to claim 13 , further comprising performing a laser anneal after providing the high-k dielectric layer.
20. The method according to claim 13 , wherein the method is a gate-last manufacturing method in which a final gate electrode is formed by replacing a sacrificial gate electrode.
21. The FET according to claim 1 , wherein the interfacial dielectric layer comprises a thermal SiO x .
22. The method according to claim 13 , wherein separately depositing the dielectric capping layer comprises forming an interface dipole by the dielectric capping layer as deposited at an interface between the interfacial dielectric layer and the dielectric capping layer.
23. The FET according to claim 1 , wherein the dielectric capping layer comprises LaSiO, the high-k dielectric layer comprises HfO 2 , and the gate electrode layer comprises TiN.
24. The method according to claim 13 , wherein the dielectric capping layer comprises LaSiO, the high-k dielectric layer comprises HfO 2 , and the gate electrode layer comprises TiN.