IP Library Granted Patent US 10,680,109
Granted Patent B2
US 10,680,109 · App. 16/141,509 · Granted Jun 9, 2020

CMOS semiconductor device having fins and method of fabricating the same

Inventors: Shu-Hao Kuo (Tainan, TW); Jung-Hao Chang (Taichung, TW); Chao-Hsien Huang (Tainan, TW); Li-Te Lin (Hsinchu, TW); Kuo-Cheng Ching (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/7853H01L21/3065H01L21/30604H01L21/31116H01L21/76229H01L21/823821H01L21/845H01L27/0924H01L27/1211H01L29/0649H01L29/41791H01L29/66795H01L29/66803H01L21/0262H01L21/02532H01L2029/7858
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Quick Facts
Patent No.
US 10,680,109
App. No.
16/141,509
Granted
Jun 9, 2020
Kind
B2
Abstract

A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

Claims (46)

1. A method, comprising:

bonding a first semiconductor substrate onto a second semiconductor substrate with an insulator layer between the first semiconductor substrate and the second semiconductor substrate;

etching the first semiconductor substrate to form an upper portion of a fin, wherein a first portion of the insulator layer is exposed by etching the first semiconductor substrate;

depositing a protection layer over the upper portion of the fin and over a top surface of the first portion of the insulator layer using an atomic layer deposition process;

etching first portions of the protection layer over a top surface of the upper portion of the fin and the top surface of the first portion of the insulator layer, wherein a second portion of the protection layer remains on a side surface of the upper portion of the fin;

etching the first portion of the insulator layer, wherein a second portion of the insulator layer remains under the upper portion of the fin; and

etching the second semiconductor substrate to form a bottom portion of the fin under the second portion of the insulator layer.

2. The method of claim 1 , further comprising:

etching the second portion of the protection layer.

3. The method of claim 1 , wherein etching the first semiconductor substrate and etching the first portion of the insulator layer use different etchants.

4. The method of claim 1 , wherein etching the first semiconductor substrate uses a chlorine-based etchant.

5. The method of claim 1 , wherein etching the first portion of the insulator layer uses a fluorine-based etchant.

6. The method of claim 1 , wherein etching the first portion of the insulator layer and etching the second semiconductor substrate use different etchants.

7. The method of claim 1 , wherein etching the second semiconductor substrate uses a chlorine-based etchant.

8. The method of claim 1 , wherein the protection layer has a thickness in a range from about 2 nm to about 3 nm.

9. A method, comprising:

bonding a first semiconductor substrate onto a second semiconductor substrate with an insulator layer between the first semiconductor substrate and the second semiconductor substrate;

etching a first portion of the first semiconductor substrate and a first portion of the insulator layer until the second semiconductor substrate is exposed, wherein a second portion of the first semiconductor substrate and a second portion of the insulator layer remain over the second semiconductor substrate;

epitaxially growing an epitaxy layer over the second semiconductor substrate;

etching the second portion of the first semiconductor substrate to form an upper portion of a first fin and etching the epitaxy layer to form an upper portion of a second fin, wherein a first sub-portion of the second portion the insulator layer is exposed by etching the second portion of the first semiconductor substrate;

depositing a protection layer over the upper portion of the second fin using an atomic layer deposition process;

etching the first sub-portion of the second portion of the insulator layer, wherein a second sub-portion of the second portion of the insulator layer remains under the upper portion of the first fin; and

etching the second semiconductor substrate to form a bottom portion of the first fin under the second sub-portion of the second portion of the insulator layer and a bottom portion of the second fin under the upper portion of the second fin.

10. The method of claim 9 , further comprising:

removing the protection layer from the upper portion of the second fin.

11. The method of claim 9 , wherein etching the epitaxy layer and etching the first sub-portion of the second portion of the insulator layer use different etchants.

12. The method of claim 9 , wherein depositing the protection layer is performed such that the protection layer is deposited over the upper portion of the first fin.

13. The method of claim 9 , wherein etching the first sub-portion of the second portion of the insulator layer is performed using plasma bombardment.

14. A method, comprising:

forming a P-type well and an N-type well in a first substrate;

bonding a second substrate onto the first substrate with an oxide layer between the first substrate and the second substrate;

patterning the second substrate into a patterned second substrate over the P-type well, and the oxide layer into a patterned oxide layer vertically between the P-type well and the patterned second substrate;

after patterning the second substrate and the oxide layer, epitaxially growing an epitaxy layer from the N-type well;

patterning the patterned second substrate into upper portions of first fins and the epitaxy layer into upper portions of second fins;

forming a protection layer over the upper portions of the first fins and the upper portions of the second fins;

performing a plasma etching process on the protection layer until the patterned oxide layer is broken into separate oxide strips; and

patterning the first substrate within the P-type well into bottom portions of the first fins using the oxide strips as an etch mask.

15. The method of claim 14 , further comprising:

after patterning the first substrate within the P-type well, removing the protection layer from side surfaces of the upper portions of the first fins.

16. The method of claim 14 , further comprising:

after patterning the first substrate within the P-type well, removing the protection layer from side surfaces of the upper portions of the second fins.

17. The method of claim 14 , further comprising:

patterning the first substrate within the N-type well into bottom portions of the second fins.

18. The method of claim 17 , wherein patterning the first substrate within the N-type well is performed simultaneously with patterning the first substrate within the P-type well.

19. The method of claim 14 , wherein the plasma etching process uses a different chemistry than that of patterning the second substrate.

20. The method of claim 14 , wherein the plasma etching process uses a fluorine-based chemistry.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2018
From: KUO, SHU-HAO; CHANG, JUNG-HAO; HUANG, CHAO-HSIEN; LIN, LI-TE; CHING, KUO-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 047661/0069 →
Continuity (2)
Provisional Application 62565020 · Sep 28, 2017
Related Publication 20190097056A1 · Mar 28, 2019