Modem chip for performing hybrid automatic repeat request processing, application processor including the modem chip, and operating method of the modem chip

1. A modem chip comprising:

a hybrid automatic repeat request (HARQ) controller configured to control an operation for saving HARQ data;

a HARQ combiner configured to combine retransmission data with the HARQ data;

an internal memory configured to save at least one of a plurality of HARQ data; and

the HARQ controller is configured to save the HARQ data in the internal memory or an external memory disposed outside the modem chip, based on information on component carriers used in a communication network.

2. The modem chip of claim 1 , wherein the information on component carriers is a number of activated component carriers used in the communication network.

3. The modem chip of claim 2 , wherein the HARQ controller is configured to:

save the HARQ data in the internal memory in response to the number of activated component carriers being less than a reference number; and

save the HARQ data in the external memory in response to the number of activated component carriers being equal to or greater than the reference number.

4. The modem chip of claim 3 , wherein the HARQ controller is configured to:

save the HARQ data in the internal memory in response to one component carrier being activated; and

save the HARQ data in the external memory in response to two or more component carriers being activated.

5. The modem chip of claim 1 , wherein

the modem chip is configured to determine a channel performance of the communication network; and

the HARQ controller is configured to control the HARQ data not to be saved in the internal memory and the external memory in response to the channel performance being worse than a reference performance.

6. The modem chip of claim 1 , wherein the internal memory includes a buffer region configured to temporarily save the HARQ data fetched from the external memory.

7. The modem chip of claim 1 , wherein

the modem chip is configured to receive a plurality of codeword data; and

the HARQ controller is configured to save the HARQ data corresponding to a part of the plurality of codeword data in the internal memory or the external memory, based on a cyclic redundancy check (CRC) check result with respect to the plurality of codeword data.

8. The modem chip of claim 1 , wherein, in response to the HARQ data being saved in the external memory, the HARQ controller is configured to:

determine whether a timeout occurs when the HARQ data is fetched from or saved in the external memory; and

control a HARQ combining operation of the HARQ combiner based on a results of the timeout determination.

9. An application processor comprising:

a processing core;

a memory interface configured to operate as an interface with respect to an external memory; and

a modem circuit connected to the processing core through a system bus, and configured to

receive a plurality of codeword data, each of the plurality of codeword data including a plurality of codeblock data,

control a first part of a plurality of HARQ data to be saved in the external memory based on an error detection result associated with the plurality of codeword data, and

combine retransmission data with the HARQ data.

10. The application processor of claim 9 , further comprising:

an internal memory configured to save a second part of the plurality of HARQ data.

11. The application processor of claim 10 , wherein the modem circuit is configured to save the HARQ data in the internal memory or the external memory, according to a number of activated component carrier used in a communication network.

12. The application processor of claim 9 , wherein, in response to the HARQ data being saved in the external memory, the modem circuit is configured to:

determine whether a timeout occurs when the HARQ data is fetched from or saved in the external memory; and

control a HARQ combining operation based on results of the timeout determination.

13. The application processor of claim 9 , wherein the modem circuit is configured to:

receive priority information about the external memory occupation via the system bus under a control of the processing core; and

control an access timing for the external memory based on the priority information.

14. An operating method of a modem chip, the method comprising:

receiving data including at least one codeword unit, the at least one codeword unit including a plurality of codeblock units;

performing an error detection operation on the plurality of codeblock units and the at least one codeword unit of the received data;

in response to an error detection result of at least one of the plurality of codeblock units and the at least one codeword unit indicating failure, saving HARQ data corresponding to the data of the at least one codeword unit in an external memory; and

fetching the HARQ data from the external memory to combine the HARQ data with retransmitted data.

15. The method of claim 14 , wherein the performing of the error detection comprises:

performing a cyclic redundancy check (CRC) check operation on each of the plurality of codeblock units included in the at least one codeword unit; and

performing a CRC check operation on the at least one codeword unit.

16. The method of claim 14 , further comprising:

determining whether the HARQ data is normally fetched within a desired time after the fetching of the HARQ data starts; and

determining whether a timeout occurs while the HARQ data is being fetched, based on a result of the determination of whether the HARQ data is normally fetched.

17. The method of claim 16 , the method further comprising:

in response to determining that the timeout does not occur, performing a HARQ combining operation for combining the normally fetched HARQ data with the retransmitted data; and

in response to determining that the timeout occurs, processing the retransmitted data as initially transmitted data.

18. The method of claim 14 , wherein the modem chip includes an internal memory, and the method further comprises:

determining a number of component carriers used for data communication with an external transmission system; and

saving the HARQ data in the internal memory based on the determined number of component carriers.