Memory system and operating method thereof

1. A method for operating a memory system, the method comprising:

generating a write request for write data;

reading chunk data from a buffer memory in response to the write request;

caching the chunk data in a cache memory;

generating a read request for read data; and

outputting a portion of the cached chunk data as the read data from the cache memory when the read data is included in the cached chunk data.

2. The method of claim 1 , further comprising:

modifying the cached chunk data based on the write data; and

writing the modified chunk data in the buffer memory after outputting the read data.

3. The method of claim 2 , further comprising:

reading parity data corresponding to the chunk data; and

performing an error correction code (ECC) decoding operation based on the chunk data and the parity data.

4. The method of claim 3 , wherein caching the chunk data includes caching the ECC-decoded chunk data in the cache memory.

5. The method of claim 2 , wherein writing the modified chunk data includes:

generating error correction code (ECC)-encoded chunk data and parity data by performing an ECC encoding operation on the modified chunk data; and

writing the ECC-encoded chunk data and the parity data in the buffer memory.

6. The method of claim 1 , wherein the chunk data includes logical-physical address mapping information on a nonvolatile memory device.

7. The method of claim 1 , further comprising:

receiving a write command and a logical address from a host; and

allocating a physical address of a nonvolatile memory device in response to the write command, the physical address corresponding to the logical address,

wherein the write data includes mapping information between the logical address and the physical address.

8. The method of claim 1 , further comprising receiving a read command and a logical address from a host,

wherein the read data includes information on a physical address of a nonvolatile memory device, the physical address corresponding to the logical address.

9. The method of claim 1 , wherein the cached chunk data in the cache memory is first chunk data, the method further comprising:

reading second chunk data including the read data and parity data corresponding to the second chunk data from the buffer memory when the read data is not included in the first chunk data cached in the cache memory;

performing an error correction code (ECC) decoding operation based on the second chunk data and the parity data; and

caching the ECC-decoded second chunk data in the cache memory; and

outputting a portion of the second chunk data as the read data.

10. The method of claim 9 , further comprising:

modifying the cached first chunk data based on the write data; and

writing the modified first chunk data in the buffer memory after outputting the portion of the second chunk data as the read data.

11. A method for operating a memory system, the method comprising:

generating a write request for write data;

reading first chunk data from a buffer memory in response to the write request and caching the read first chunk data in a cache memory;

generating a read request for read data;

reading second chunk data from the buffer memory in response to the read request and caching the read second chunk data in the cache memory;

outputting a portion of the cached second chunk data as the read data;

modifying the cached first chunk data based on the write data; and

writing the modified first chunk data in the buffer memory after outputting the read data.

12. The method of claim 11 , further comprising:

reading parity data corresponding to the first chunk data; and

performing an error correction code (ECC) decoding operation based on the first chunk data and the parity data.

13. The method of claim 11 , further comprising generating parity data by performing an error correction code (ECC) encoding operation on the modified first chunk data.

14. The method of claim 11 , wherein one or both of the first chunk data and the second chunk data include logical-physical address mapping information on a nonvolatile memory device.

15. The method of claim 11 , wherein the buffer memory includes a Dynamic Random Access Memory (DRAM), and the cache memory includes a Static Random Access Memory (SRAM).