Method and device for on-chip repetitive addressing
View Patent ↗A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.
1. An on-chip repetitive addressing method, comprising:
a data partitioning step for partitioning data on an on-chip storage medium and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein the pre-determined data partition principle partitions the data with a reuse distance less than a pre-determined distance threshold value into same data block; and
a data indexing step for successively loading the different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing;
wherein an index address for a data is consisted of a data block address and an in-block address;
the data indexing step comprises successively loading different data blocks to the at least one on-chip processing unit according to the pre-determined ordinal relation of the replacement policy and the data block address, wherein the repeated data in the loaded data block being subjected to on-chip repetitive addressing, and when all indexing of the in-block address of the data block are completed, a new data block is loaded until all of the data blocks have been load.
2. The on-chip repetitive addressing method according to claim 1 , wherein the on-chip repetitive addressing method is applied to a learning accelerator; and/or
the method is applied to a heterogeneous environment, and the heterogeneous environment is a multichip architecture including a CPU and a learning accelerator;
the on-chip storage medium exchanges data with the on-chip processing unit through an on-chip data path;
the on-chip storage medium exchanges data with the off-chip storage medium through a data path to connect the on-chip storage media and the off-chip storage media, and the on-chip storage medium or the off-chip storage medium performs at least one reading and writing from inside of the learning accelerator or outside of the learning accelerator;
the data is carried between the on-chip storage medium, the off-chip storage medium and/or the on-chip processing unit in a unit of data block.
3. The on-chip repetitive addressing method according to claim 1 , wherein a data size of a data block is smaller than a capacity of the on-chip storage medium.
4. The on-chip repetitive addressing method according to claim 1 , wherein the on-chip storage medium adopts a design in which a read port is separated from a write port.
5. The on-chip repetitive addressing method according to claim 1 , wherein the on-chip processing unit is an on-chip operation module, a data is selected according to a pre-determined condition, and the data satisfying the pre-determined condition is partitioned into the same data block.
6. The on-chip repetitive addressing method according to claim 5 , wherein the pre-determined condition comprises a simple partitioning condition, a condition with an average pre-determined number of data blocks, a condition associated with different output neurons, or a condition satisfying a pre-determined mathematic relation.
7. The on-chip repetitive addressing method according to claim 5 , wherein the replacement policy comprises an ordinal replacement, a reversed replacement or an unordered replacement; or
the replacement policy comprises data writing back, which writes a final result or an intermediate result back to the on-chip storage medium, the off-chip storage medium and/or the on-chip processing unit after the data is processed.
8. A device for on-chip repetitive addressing, the device comprising:
a data partitioning module for partitioning data on an on-chip storage medium and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein the pre-determined data partitioning principle partitions the data with a reuse distance less than a pre-determined distance threshold value into same data block;
a data indexing module for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing;
wherein an index address for a data is consisted of a data block address and an in-block address;
the data indexing step comprises successively loading different data blocks to the at least one on-chip processing unit according to the pre-determined ordinal relation of the replacement policy and the data block address, wherein the repeated data in the loaded data block being subjected to on-chip repetitive addressing, and when all indexing of the in-block address of the data block are completed, a new data block is loaded until all of the data blocks have been loaded.
9. The device for on-chip repetitive addressing according to claim 8 , wherein the method is applied to a learning accelerator; and/or
the method is applied to a heterogeneous environment, and the heterogeneous environment is a multichip architecture including a CPU and a learning accelerator;
the on-chip storage medium exchanges data with the on-chip processing unit through an on-chip data path;
the on-chip storage medium exchanges data with the off-chip storage medium through a data path to connect the on-chip storage medium and the off-chip storage medium, and the on-chip storage medium or the off-chip storage medium performs at least one reading and writing from inside of the learning accelerator or outside of the learning accelerator;
the data is carried between the on-chip storage medium, the off-chip storage medium and/or the on-chip processing unit in a unit of data block.
10. The device for on-chip repetitive addressing according to claim 8 , wherein a data size of a data block is smaller than a capacity of the on-chip storage medium.
11. The device for on-chip repetitive addressing according to claim 8 , wherein the on-chip storage medium adopts a design in which a read port is separated from a write port.
12. The device for on-chip repetitive addressing according to claim 8 , wherein the on-chip processing unit is an on-chip operation module, a data is selected according to a pre-determined condition, and the data satisfying the pre-determined condition is partitioned into the same data block.
13. The device for on-chip repetitive addressing according to claim 12 , wherein the pre-determined condition comprises a simple partitioning condition, a condition with an average pre-determined number of data blocks, a condition associated with different output neurons, or a condition satisfying a pre-determined mathematic relation.
14. The device for on-chip repetitive addressing according to claim 13 , wherein the replacement policy comprises an ordinal replacement, a reversed replacement or an unordered replacement; or
the replacement policy comprises data writing back, which writes a final result or an intermediate result back to the on-chip storage medium, the off-chip storage medium and/or the on-chip processing unit after the data is processed.