IP Library › Granted Patent US 10,685,689

Granted Patent B2

US 10,685,689 · App. 16/259,259 · Granted Jun 16, 2020

Semiconductor memory device

Inventor: Hiroki Date (Kanagawa, JP)

G11C7/22 G11C16/08 G11C16/10 G11C16/28 G11C16/32 H01L27/1157 H01L27/11573 H01L27/11582 H01L27/11524 H01L27/11526 H01L27/11556

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Quick Facts

Patent No.: US 10,685,689
App. No.: 16/259,259
Granted: Jun 16, 2020
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.

Claims (79)

1. A semiconductor memory device comprising:

a substrate;

a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other;

a first wiring connected to a gate electrode of the first memory transistor; and

a second wiring connected to a gate electrode of the first selection transistor, wherein

in a write operation performed to the first memory transistor,

at a first timing, a voltage of the first wiring rises,

at a second timing after the first timing, the voltage of the first wiring falls,

at a third timing after the second timing, a voltage of the second wiring rises,

at the third timing or at a fourth timing after the third timing, the voltage of the first wiring rises,

at a fifth timing after the voltage of the first wiring rises at the third timing or the fourth timing, the voltage of the second wiring falls, and

at a sixth timing after the fifth timing, the voltage of the first wiring falls.

2. The semiconductor memory device according to claim 1 , wherein,

at a seventh timing after the sixth timing, the voltage of the first wiring rises.

3. The semiconductor memory device according to claim 1 , wherein,

at an eighth timing between the first timing and the second timing, the voltage of the first wiring further rises, and

at a ninth timing between the eighth timing and the second timing, the voltage of the first wiring falls.

4. The semiconductor memory device according to claim 1 , wherein,

the amount of decrease of the voltage of the first wiring falling at the second timing and the amount of increase of the voltage of the first wiring rising at the third timing or the fourth timing are smaller than the amount of increase of the voltage of the first wiring rising at the first timing and the amount of decrease of the voltage of the first wiring falling at the sixth timing.

5. The semiconductor memory device according to claim 1 , further comprising:

a first transistor connected to the first wiring; and

a third wiring connected to the first transistor, wherein

at the first timing, a voltage of the third wiring rises,

at the second timing, the voltage of the third wiring falls,

at the third timing or the fourth timing, the voltage of the third wiring rises, and

at the sixth timing, the voltage of the third wiring falls.

6. The semiconductor memory device according to claim 5 , wherein,

at a seventh timing after the sixth timing, the voltage of the first wiring rises, and

the voltage of the first wiring after the rise at the seventh timing is larger than the voltage of the third wiring at the seventh timing.

7. A semiconductor memory device comprising:

a substrate;

a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other;

a first wiring connected to a gate electrode of the first memory transistor; and

a second wiring connected to a gate electrode of the first selection transistor, wherein

in a write operation performed to the first memory transistor,

at a first timing, a voltage of the first wiring rises,

at a second timing after the first timing, a voltage of the second wiring rises,

at a third timing after the second timing, the voltage of the second wiring further rises,

at a fourth timing after the third timing, the voltage of the second wiring falls, and

at a fifth timing after the fourth timing, the voltage of the first wiring falls.

8. The semiconductor memory device according to claim 7 , wherein,

at a sixth timing after the fifth timing, the voltage of the first wiring rises.

9. The semiconductor memory device according to claim 7 , wherein,

at a seventh timing between the first timing and the second timing, the voltage of the first wiring further rises, and

at an eighth timing between the seventh timing and the second timing, the voltage of the first wiring falls.

10. The semiconductor memory device according to claim 7 , wherein,

the amount of increase of the voltage of the second wiring rising at the second timing and the amount of increase of the voltage of the second wiring rising at the third timing are smaller than the amount of decrease of the second wiring falling at the fourth timing.

11. The semiconductor memory device according to claim 7 , further comprising:

a first transistor connected to the first wiring; and

a third wiring connected to the first transistor, wherein

at the first timing, a voltage of the third wiring rises,

at the fifth timing, the voltage of the third wiring falls,

at a sixth timing after the fifth timing, the voltage of the first wiring rises, and

the voltage of the first wiring after the rise at the sixth timing is larger than the voltage of the third wiring at the sixth timing.

12. A semiconductor memory device comprising:

a substrate;

a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other;

a first wiring connected to a gate electrode of the first memory transistor;

a second wiring connected to a gate electrode of the first selection transistor; and

a third wiring connected a drain electrode of the first selection transistor, wherein

in a write operation performed to the first memory transistor,

at a first timing, a voltage of the first wiring rises,

at a second timing after the first timing, a voltage of the third wiring rises,

at a third timing after the second timing, a voltage of the second wiring rises,

at a fourth timing after the third timing, the voltage of the third wiring falls,

at a fifth timing after the fourth timing, the voltage of the second wiring falls, and

at a sixth timing after the fifth timing, the voltage of the first wiring falls.

13. The semiconductor memory device according to claim 12 , wherein,

at a seventh timing after the sixth timing, the voltage of the first wiring rises.

14. The semiconductor memory device according to claim 12 , wherein,

at an eighth timing between the first timing and the second timing, the voltage of the first wiring further rises, and

at a ninth timing between the eighth timing and the second timing, the voltage of the first wiring falls.

15. The semiconductor memory device according to claim 12 , further comprising:

a first transistor connected to the first wiring; and

a fourth wiring connected to the first transistor, wherein

at the first timing, a voltage of the fourth wiring rises,

at the sixth timing, the voltage of the fourth wiring falls,

at a seventh timing after the sixth timing, the voltage of the first wiring rises, and

the voltage of the first wiring after the rise at the seventh timing is larger than the voltage of the fourth wiring at the seventh timing.

Assignments (2)

CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021

From: TOSHIBA MEMORY CORPORATION

To: KIOXIA CORPORATION

Reel/Frame 055669/0001 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2019

From: DATE, HIROKI

To: TOSHIBA MEMORY CORPORATION

Reel/Frame 048156/0385 →

Priority Claims (1)

JP 2018-166583 · Sep 6, 2018 · national

Continuity (1)

Related Publication 20200082855A1 · Mar 12, 2020

Cited By (5)

US 12,354,677 US 12,531,120 US 12,626,738 US 12,633,348 US 12,682,966