Memory device in which locations of registers storing fail addresses are merged

1. A memory device comprising:

a bank including first memory cells connected to a first column selection line and second memory cells connected to a second column selection line;

a first column decoder configured to select the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line; and

a second column decoder configured to select the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line,

wherein the first column decoder includes:

a first register configured to store a first fail column address of the first memory cells; and

a second register configured to store a second fail column address of the second memory cells.

2. The memory device of claim 1 , wherein the first column decoder further includes:

a compare circuit configured to compare an input column address with one of the first fail column address and the second fail column address.

3. The memory device of claim 2 , wherein the first column decoder is configured to:

generate a first hit signal based on a result of comparing the input column address with the first fail column address; and

select first redundancy memory cells by using the first hit signal instead of memory cells corresponding to the first fail column address among the first memory cells.

4. The memory device of claim 2 , wherein the first column decoder is configured to:

generate a second hit signal based on a result of comparing the input column address with the second fail column address; and

transmit the second hit signal to the second column decoder, and

wherein the second column decoder is configured to:

select second redundancy memory cells by using the second hit signal instead of memory cells corresponding to the second fail column address among the second memory cells.

5. The memory device of claim 2 , further comprising:

a command decoder configured to transmit the input column address to the first column decoder and the second column decoder,

wherein the command decoder is positioned more adjacent to the first column decoder than the second column decoder.

6. The memory device of claim 1 , further comprising:

an anti-fuse array in which the first fail column address and the second fail column address are programmed,

wherein the first column decoder further includes:

a write circuit configured to write the first fail column address transmitted from the anti-fuse array to the first register and to write the second fail column address transmitted from the anti-fuse array to the second register.

7. The memory device of claim 1 , wherein the bank further includes:

third memory cells connected to a first word line and selected by the first column decoder; and

fourth memory cells connected to the first word line and selected by the second column decoder,

wherein the first column decoder further includes:

a third register configured to store a third fail column address of the third memory cells and the fourth memory cells; and

a compare circuit configured to compare an input column address with the third fail column address,

wherein the first column decoder is configured to:

generate a third hit signal based on a result of comparing the input column address with the third fail column address;

transmit the third hit signal to the second column decoder; and

select third redundancy memory cells by using the third hit signal instead of memory cells corresponding to the third fail column address among the third memory cells, and

wherein the second column decoder is configured to:

select fourth redundancy memory cells by using the third hit signal transmitted from the first column decoder instead of memory cells corresponding to the third fail column address among the fourth memory cells.

8. The memory device of claim 1 , wherein the bank further includes:

fifth memory cells connected to a second word line and selected by the first column decoder; and

sixth memory cells connected to a third word line, which is selected at the same time with the second word line, and selected by the second column decoder,

wherein the first column decoder further includes:

a fourth register configured to store a fourth fail column address of the fifth memory cells and the sixth memory cells; and

a compare circuit configured to compare an input column address with the fourth fail column address,

wherein the first column decoder is configured to:

generate a fourth hit signal based on a result of comparing the input column address with the fourth fail column address;

transmit the fourth hit signal to the second column decoder; and

select fifth redundancy memory cells by using the fourth hit signal instead of memory cells corresponding to the fourth fail column address among the fifth memory cells, and

wherein the second column decoder is configured to:

select sixth redundancy memory cells by using the fourth hit signal transmitted from the first column decoder instead of memory cells corresponding to the fourth fail column address among the sixth memory cells.

9. The memory device of claim 1 , wherein input/output lines of the first memory cells and the second memory cells are arranged in the bank, and

wherein the first column decoder performs data input/output on the first memory cells and the second memory cells through the input/output lines.