Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability
Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
1. A method of forming an interconnect stack, the method comprising:
forming a first dielectric layer;
forming a first trench in the first dielectric layer;
depositing a first liner in the first trench, wherein the first liner defines a second trench;
depositing a first conductive material in the second trench;
depositing a second dielectric layer over the first dielectric layer and the first conductive material, wherein the second dielectric layer comprises a first region and a second region;
forming a third trench extending through the second dielectric layer and over the first conductive material;
wherein a first region of the third trench is within the first region of the second dielectric layer;
wherein a second region of the third trench is within the second region of the second dielectric layer;
exposing at least a portion of a top surface of the first conductive material, wherein a bottom surface of the third trench comprises the exposed portion of the top surface of the first conductive material; and
depositing a second liner in the first region and the second region of the third trench;
wherein the second liner is on sidewalls of the third trench;
wherein the second liner that is in the first region of the third trench is a different material than the second liner that is in the second region of the third trench;
wherein the second liner is also on the exposed portion of the top surface of the first conductive material; and
wherein the second liner that is on the exposed portion of the top surface of the first conductive material functions as a cap region configured to counter electro-migration or surface migration at the top surface of the first conductive material.
2. The method of claim 1 further comprising depositing a cap layer over a top surface of the first conductive material, wherein exposing the portion of the top surface of the first conductive material comprises removing at least a portion of the cap layer.
3. The method of claim 1 , wherein:
the second liner defines a fourth trench;
the method further comprises depositing a second conductive material in the fourth trench; and
the second liner adheres a portion of the second conductive material to the second dielectric layer.
4. The method of claim 3 further comprising depositing a third dielectric layer over the second dielectric layer and the second conductive material.
5. The method of claim 4 further comprising forming a fifth trench extending through the third dielectric layer and over the second conductive material.
6. The method of claim 5 further comprising exposing at least a portion of the top surface of the second conductive material, wherein a bottom surface of the fifth trench comprises the exposed portion of the top surface of the second conductive material.
7. The method of claim 6 further comprising depositing a cap layer over a top surface of the second conductive material, wherein exposing the portion of the top surface of the second conductive material comprises removing at least a portion of the cap layer.
8. The method of claim 6 further comprising:
depositing a third liner in the fifth trench;
wherein the third liner is on sidewalls of the fifth trench;
wherein the third liner is also on the exposed portion of the top surface of the second conductive material; and
wherein the third liner that is on the exposed portion of the top surface of the second conductive material functions as a cap region configured to counter electro-migration or surface migration at the top surface of the second conductive material.
9. The method of claim 8 , wherein the third liner defines a sixth trench.
10. The method of claim 9 further comprising:
depositing a third conductive material in the sixth trench; and
depositing a cap layer over an exposed surface of the third conductive material;
wherein a bottom region of the first liner is communicatively coupled to a source region of a transistor or a drain region of the transistor.
11. A method of forming an interconnect stack, the method comprising:
forming a first dielectric layer;
forming a first trench in the first dielectric layer;
depositing a first liner in the first trench, wherein the first liner defines a second trench;
depositing a first conductive material in the second trench;
depositing a second dielectric layer over the first dielectric layer and the first conductive material, wherein the second dielectric layer comprises a first region and a second region;
forming a third trench extending through the first and second regions of the second dielectric layer and over the first conductive material;
wherein a first region of the third trench is within the first region of the second dielectric layer;
wherein a second region of the third trench is within the second region of the second dielectric layer;
wherein a volume of the first region of the third trench is different than a volume of the second region of the third trench;
exposing at least a portion of the top surface of the first conductive material, wherein a bottom surface of the third trench comprises the exposed portion of the top surface of the first conductive material; and
depositing a second liner in the first region and the second region of the third trench;
wherein the second liner that is in the first region of the third trench is a different material than the second liner that is in the second region of the third trench;
wherein the second liner is on sidewalls of a first portion of the third trench;
wherein the second liner is also on sidewalls of a second portion of the third trench;
wherein the second liner is also on the exposed portion of the top surface of the first conductive material; and
wherein the second liner that is on the exposed portion of the top surface of the first conductive material functions as a cap region configured to counter electro-migration or surface migration at the top surface of the first conductive material.
12. The method of claim 11 further comprising depositing a cap layer over a top surface of the first conductive material, wherein exposing at least the portion of the top surface of the first conductive material comprises removing a portion of the cap layer.
13. The method of claim 11 further comprising depositing a second conductive material in the first region of the third trench, wherein the second liner adheres a portion of the second conductive material to the first region of the second dielectric layer.
14. The method of claim 13 , wherein a bottom surface of the second region of the third trench comprises a top surface of the second conductive material.
15. The method of claim 14 further comprising:
depositing a third conductive material in the second region of the third trench; and
depositing a cap layer over an exposed surface of the third conductive material;
wherein a bottom region of the first liner is communicatively coupled to a source region of a transistor or a drain region of the transistor.
16. The method of claim 15 , wherein
the second conductive material is the same material as the third conductive material.
17. The method of claim 15 , wherein
the second conductive material is a different material than the third conductive material.