IP Library Granted Patent US 10,685,907
Granted Patent B2
US 10,685,907 · App. 16/417,589 · Granted Jun 16, 2020

Semiconductor structure with through silicon via and method for fabricating and testing the same

Inventor: Hsueh-Hao Shih (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L23/481H01L22/14H01L22/30H01L22/32H01L24/05
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Quick Facts
Patent No.
US 10,685,907
App. No.
16/417,589
Granted
Jun 16, 2020
Kind
B2
Abstract

A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided.

Claims (12)

1. A fabricating method of a semiconductor structure with a through silicon via, comprising:

providing a substrate comprising a front side and a back side;

forming a device disposed on the front side of the substrate;

forming a through silicon via embedded in the substrate, wherein an end of the through silicon via is entirely covered by the back side of the substrate;

forming a plurality of dielectric layers on the front side of the substrate;

forming a first test pad on a surface of the dielectric layers and the first test pad electrically connecting to the device;

testing the first test pad;

after testing the first test pad,

thinning the back side of the substrate to expose the end of the through silicon via;

forming a second test pad disposed on the back side of the substrate and the second test pad electrically connecting to the through silicon via; and

after thinning the back side of the substrate, testing the second test pad to determine if the through silicon via works and and/or to determine if the through silicon via can pass a reliability test.

2. The fabricating method of a semiconductor structure with a through silicon via of claim 1 , further comprising an inner circuit disposed in the dielectric layers wherein the inner circuit electrically connects to the device and the through silicon via.

Continuity (2)
Division 14174850 · Feb 7, 2014
Related Publication 20190273033A1 · Sep 5, 2019