Semiconductor device and manufacturing method thereof
A semiconductor device includes a wiring structure, a stacked structure located over the wrong structure, channel structures passing through the stacked structure, contact plugs passing through the stacked structure and electrically connected to the wiring structure, and insulating spacers each including loop patterns surrounding a sidewall of each of the contact plugs and stacked along the side all of each of the contact plugs.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a wiring structure in an interlayer insulating layer;
forming a stacked structure including first material layers and second material layers stacked alternately with each other on the wiring structure;
forming first openings passing through the stacked structure;
forming second openings by partially etching each of the first material layers through the first openings;
forming insulating spacers each including loop patterns located in the second openings; and
forming contact plugs electrically coupled to the wiring structure in the first openings,
wherein the loop patterns surround sidewalk of the contact plugs which are electrically coupled to a peripheral circuit through the wiring structure.
2. The method of claim 1 , wherein each of the insulating spacers includes the loop patterns in the second openings and a coupling pattern in each of the first openings.
3. The method of claim 1 , wherein the forming of the insulating spacers comprises:
forming an insulating layer in the first and second openings; and
forming the loop patterns by etching the insulating layer using a dry cleaning process.
4. The method of claim 1 , wherein the forming of the insulating spacers comprises:
forming a first insulating layer in the first and second openings;
forming second insulting patterns located in the second openings, respectively; and
forming first insulating patterns located in the second openings, respectively, by etching the first insulating layer using the second insulating patterns as an etch barrier.
5. The method of claim 1 , wherein the forming of the second openings comprises controlling an etch depth of the first material layers so that neighboring first openings are coupled to each other.
6. The method of claim 1 , wherein the forming of the second openings comprises controlling an etch depth of the first material layers so that neighboring first openings are separated from each other.
7. A method of manufacturing a semiconductor device, the method comprising:
forming a wiring structure;
forming a stacked structure including first material layers and second material layers stacked alternately with each other on the wiring structure;
forming first openings passing through the stacked structure;
forming second openings by partially etching the first material layers exposed through the first openings;
forming insulating spacers each including loop patterns located in the second openings;
forming contact plugs electrically coupled to the wiring structure in the first openings; and
forming an isolation pattern partially passing through the stacked structure and extending in one direction,
wherein the isolation pattern is coupled to the insulating spacers.
8. A method of manufacturing a semiconductor device, the method comprising:
forming an interconnection structure in an interlayer insulating layer;
forming a stacked structure over the interlayer insulating layer;
forming first openings passing through the stacked structure;
forming second openings, wherein the second openings are coupled to each of the first openings and protruding from sidewalk of the first openings;
forming spacers each including loop patterns filling the second openings; and
forming plugs in the first openings,
wherein the second openings of neighboring first openings are coupled to each other, and
wherein the loop patterns surround sidewalk of the plugs which are electrically coupled to a peripheral circuit through the interconnection structure.
9. The method of claim 8 , wherein the forming of the spacers comprises forming the loop patterns filling the second openings, respectively, and a coupling pattern in the first openings.
10. The method of claim 8 , wherein the forming of the spacers comprises:
forming an insulating layer in the first and second openings; and
forming the loop patterns filling the second openings, respectively, by etching the insulating layer using a dry cleaning process.
11. The method of claim 8 , wherein the forming of the spacers comprises:
forming a first insulating layer in the first and second openings;
forming second insulating patterns in the second openings, respectively; and
forming first insulating patterns located in the second openings, respectively, by etching the first insulating layer using the second insulating patterns as an etching barrier.
12. The method of claim 8 , wherein the stacked structure includes first material layers and second material layers stacked alternately with each other, and the second openings are formed by selectively etching the first material layers exposed through the first openings.
13. The method of claim 8 , wherein the interconnection structure includes wires and contact plugs.
14. The method of claim 8 , wherein loop patterns of neighboring spacers are coupled to each other.
15. The method of claim 1 , wherein the contact plugs are formed after the insulating spacers are formed.