Dynamic random access memory and fabrication method thereof

1. A method for fabricating a dynamic random access memory (DRAM), comprising:

providing a base substrate;

forming a gate structure over the base substrate;

forming doped source/drain regions in the base substrate protruding from a top surface of the base substrate at two sides of the gate structure, respectively;

forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions;

forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and

forming a memory structure in the first opening and directly on the one of doped source/drain regions, wherein forming the memory structure in the first opening comprises:

forming a first conductive layer on side and bottom surfaces of the first opening;

forming a memory medium layer on side and bottom surfaces of the first conductive layer; and

forming a second conductive layer on the memory medium layer, wherein:

the first conductive layer has a top surface coplanar with a top surface of the memory medium layer, a top surface of the second conductive layer, and a top surface of the interlayer dielectric layer, and

the first conductive layer is directly on and electrically connected with the one of doped source/drain regions.

2. The method according to claim 1 , wherein:

the gate structure includes a first side and a second side opposing the first side;

the first side and the second side expose the doped source/drain regions, respectively.

3. The method according to claim 2 , wherein:

when a number of the doped source/drain regions at the first side of the gate structure along a direction parallel to a length direction of the gate structure is more than one, and a number of the doped source/drain regions at the second side of the gate structure along the direction parallel to the length direction of the gate structure is more than one:

more than one first conductive layer is formed;

each first conductive layer is directly on a surface of and electrically connected with a corresponding doped source or drain region at the first side of the gate structure; and

the first conductive layers are discretely distributed and electrically insulated to each other.

4. The method according to claim 3 , the first opening being at the first side of the gate structure and extending to a portion of the base substrate between adjacent doped source/drain regions along the direction parallel to the extension direction of the gate structure, wherein the first conductive layers are formed by:

forming an initial first conductive material layer on the side and bottom surfaces of the first opening and a surface of the base substrate between adjacent doped source/drain regions; and

removing portions of the initial first conductive layer on the base substrate between adjacent doped source/drain regions.

5. The method according to claim 2 , the first opening being at the first side of the gate structure, further comprising:

forming a second opening exposing the doped source/drain regions at the second side of the gate structure in the interlayer dielectric layer; and

forming a bit-line layer in the second opening, wherein the bit-line layer is discretely distributed along a direction parallel to a length direction of the gate structure.

6. The method according to claim 5 , wherein:

the first opening and the second opening are formed simultaneously.

7. The method according to claim 5 , wherein:

when a number of the doped source/drain regions at the first side of the gate structure along the direction parallel to the length direction of the gate structure is more than one and a number of the doped source/drain regions at the second side of the gate structure along the direction parallel to the length direction of the gate structure is more than one,

more than one bit-line layer is formed;

each bit-line layer is on a surface of a corresponding doped source/drain regions at the second side of the gate structure; and

the bit-line layers are discretely distributed.

8. The method according to claim 7 , the second opening extending to the base substrate between adjacent doped source/drain regions, wherein bit-line layers are formed by:

forming an initial bit-line layer on side and bottom surfaces of the second opening and a surface of the base substrate between adjacent doped source/drain regions; and

removing portions of the initial bit-line layer on the surface of the base substrate between adjacent doped source/drain regions.

9. The method according to claim 1 , wherein:

the memory structure is a resistance-change memory structure having the memory medium layer made of a resistance-change material.

10. The method according to claim 9 , wherein:

the resistance-change material includes at least one of hafnium oxide, zirconium oxide, copper oxide and zinc oxide;

the phase-change material includes at least one of chalcogenide, germanium, antimony and tellurium compound; and

the capacitive medium material includes at least one of hafnium oxide, aluminum oxide and zirconium oxide.

11. A dynamic random access memory (DRAM), comprising:

a base substrate;

a gate structure formed over the base substrate;

doped source/drain regions formed in the base substrate protruding from a top surface of the base substrate at two sides of the gate structure, respectively;

an interlayer dielectric layer formed on the gate structure, the base substrate and the doped source/drain regions, wherein the interlayer dielectric layer contains a first opening exposing the doped source/drain regions at one side of the gate structure; and

a memory structure directly on the doped source/drain regions at one side of the gate structure, having a first conductive layer on side and bottom surfaces of the first opening, a memory medium layer on the first conductive layer and a second conductive layer on the memory medium layer, formed in the interlayer dielectric layer, wherein:

the first conductive layer has a top surface coplanar with a top surface of the memory medium layer, a top surface of the second conductive layer, and a top surface of the interlayer dielectric layer, and

the first conductive layer is directly on and electrically connected with the one of doped source/drain regions.

12. The dynamic random access memory according to claim 11 , wherein:

the memory structure is one of a resistance-change structure having the memory medium layer made of a resistance-change material, a phase-change memory structure having the memory medium layer made of a phase-change material, and a capacitive memory structure having the memory medium layer made of a capacitive medium material.

13. The dynamic random access memory according to claim 12 , wherein:

the resistance-change material includes at least one of hafnium oxide, zirconium oxide, copper oxide and zinc oxide;

the phase-change material includes at least one of chalcogenide, germanium, antimony and tellurium compound; and

the capacitive medium material includes at least one of hafnium oxide, aluminum oxide and zirconium oxide.

14. The dynamic random access memory according to claim 11 , wherein:

the gate structure includes a first side and a second side opposing the first side;

the first side and the second side expose the doped source/drain regions, respectively.

15. The dynamic random access memory according to claim 14 , wherein:

when a number of the doped source/drain regions at the first side of the gate structure along a direction parallel to a length direction of the gate structure is more than one and a number of the doped source/drain regions at the second side of the gate structure along a direction parallel to the length direction of the gate structure is more than one,

more than one first conductive layer is formed;

each first conductive layer is on a surface of a corresponding doped source or drain region at the first side of the gate structure; and

the first conductive layers are distributed discretely.

16. The dynamic random access memory according to claim 14 , the first opening being at the first side of the gate structure, further comprising:

a second opening, passing through the interlayer dielectric layer and exposing the doped source/drain regions at the second side of the gate structure, formed in the interlayer dielectric layer; and

a bit-line layer formed in the second opening.

17. The dynamic random access memory according to claim 16 , wherein:

when a number of the doped source/drain regions at the first side of the gate structure along the direction parallel to the length direction of the gate structure is more than one and a number of the doped source/drain regions at the second side of the gate structure along the direction parallel to the length direction of the gate structure is more than one,

more than one bit-line layer is formed;

each bit-line layer is on a surface of a corresponding doped source/drain regions at the second side of the gate structure; and

the bit-line layers are discretely distributed.

18. The dynamic random access memory according to claim 11 , wherein the base substrate comprises:

a semiconductor substrate; and

a plurality of fins formed on the semiconductor substrate,

wherein:

the gate structure crosses over the plurality of fins; and

the doped source/drain regions are formed in the fins at two sides of the gate structure, respectively.

19. The method according to claim 1 , wherein:

the memory structure is a phase-change memory structure having the memory medium layer made of a phase-change material.

20. The method according to claim 1 , wherein:

the memory structure is a capacitive memory structure having the memory medium layer made of a capacitive medium material.