Semiconductor memory devices
A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
1. A semiconductor memory device comprising:
a first stack and a second stack on a substrate, the first stack includes a first gate electrode and a second gate electrode stacked on the substrate, the second stack includes a third gate electrode and a fourth gate electrode substantially stacked on the substrate;
vertical channel parts penetrating the first stack and the second stack;
a first conductive line connected with each of the first gate electrode and the third gate electrode;
a first array pad connecting between the second gate electrode and fourth gate electrode on the first and the second stacks; and
a second conductive line connected with the first array pad,
wherein a level of the first conductive line from a top surface of the substrate is the same with a level of the first array pad from the top surface of the substrate,
wherein a level of the second conductive line from the top surface of the substance is higher than the level of the first conductive line.
2. The semiconductor memory device of claim 1 , wherein the first conductive line extends in a first direction,
wherein the first array pad extends in a second direction crossing the first direction.
3. The semiconductor memory device of claim 1 , wherein the first stack further includes a fifth gate electrode, and
wherein the second stack further includes a sixth gate electrode,
the semiconductor memory device further comprises a second array pad connecting between the fifth gate electrode and the sixth gate electrode,
wherein the level of the first array pad is lower than a level of the second array pad from the top surface of the substrate.
4. The semiconductor memory device of claim 3 , wherein the first array pad is parallel to the second array pad.
5. The semiconductor memory device of claim 1 ,
wherein a width of the first conductive line is different from a width of the second conductive line.
6. The semiconductor memory device of claim 1 , wherein the first stack further includes a fifth gate electrode, and
wherein the second stack further includes a sixth gate electrode,
the semiconductor memory device further comprises:
a second conductive line connected with the first array pad on the first array pad; and
a third conductive line connected with the fifth gate electrode and the sixth gate electrode,
wherein the first, the second, and the third conductive lines are positioned at different levels from each other.
7. The semiconductor memory device of claim 1 , further comprising:
a second array pad connected with the first array pad on the first array pad; and
a second conductive line connected with the second array pad on the second array pad,
wherein the first conductive line and the second conductive line extends in a first direction,
wherein the first array pad and the second array pad extends in a second direction crossing the first direction.
8. A semiconductor memory device comprising:
a first stack and a second stack on a substrate, the first stack includes a first gate electrode and a second gate electrode stacked on the substrate, the second stack includes a third gate electrode and a fourth gate electrode substantially stacked on the substrate;
vertical channel parts penetrating the first stack and the second stack;
a first array pad connecting between the first gate electrode and the third gate electrode;
a second array pad connecting between the second gate electrode and the fourth gate electrode;
a first conductive line connected with the first array pad; and
a second conductive line connected with the second array pad,
wherein the first array pad and the second array pad are positioned at different levels from a top surface of the substrate,
wherein the first conductive line and the second conductive line are positioned at different levels from the top surface of the substrate,
wherein the first conductive line is disposed on a level as the second array pad, and
wherein the second conducive line is disposed on a level above the first array pad and the second array pad.
9. The semiconductor memory device of claim 8 ,
wherein the first and second conductive lines extend in a first direction,
wherein the first and second array pads extend in a second direction crossing the first direction.
10. The semiconductor memory device of claim 8 , further comprising a third array pad connected between the second array pad and the second conductive line,
wherein a level of the third array pad from the top surface of the substrate is positioned on the same level as the first conductive line.
11. The semiconductor memory device of claim 8 , wherein the first stack further includes a fifth gate electrode, and
wherein the second stack further includes sixth gate electrode,
the semiconductor memory device further comprises:
a third conductive line connected with each of the fifth gate electrode and the sixth gate electrode,
wherein a level of the third conductive line from the top surface of the substrate is positioned at a same level with the levels of the first and the second array pads, and
wherein the level of the third conductive line is lower than the levels of the first and the second conductive lines.
12. The semiconductor memory device of claim 8 , wherein the first stack further includes a fifth gate electrode, and wherein the second stack further includes sixth gate electrode, the semiconductor memory device further comprises:
a third conductive line connected with each of the fifth gate electrode and the sixth gate electrode,
wherein the first, the second, and the third conductive lines are positioned at different levels from each other.