Semiconductor structure
A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
1. A semiconductor structure, comprising:
a first standard cell including a plurality of gate strips arranged therein; and
a second standard cell including a plurality of gate strips arranged therein;
wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction; and
wherein the cell width of the first standard cell is determined according to a number of the gate strips arranged in the first standard cell, and the cell width of the second standard cell is determined according to a number of the gate strips arranged in the second standard cell; and a drivability of the first or second standard cells depends on the corresponding cell height of the first or second standard cells along a second direction perpendicular to the first direction.
2. The semiconductor structure of claim 1 , wherein the first standard cell comprises a first n-type active region and a first p-type active region disposed along the first direction, and the second standard cell comprises a second n-type active region and a second p-type active region disposed along the first direction.
3. The semiconductor structure of claim 2 , wherein the first standard cell further comprises a plurality of first gate strips passing through the first standard cell along the second direction, and the second standard cell further comprises a plurality of second gate strips passing through the second standard cell along the second direction.
4. The semiconductor structure of claim 3 , wherein a number of the first gate strips is substantially the same as a number of the second gate strips.
5. The semiconductor structure of claim 2 , wherein a width of the first n-type active region along the first direction is substantially the same as a width of the second n-type active region along the first direction, and a width of the first p-type active region along the first direction is substantially the same as a width of the second p-type active region along the first direction.
6. The semiconductor structure of claim 2 , wherein a height of the first n-type active region along the second direction is greater than a height of the second n-type active region along the second direction.
7. The semiconductor structure of claim 2 , wherein a height of the first p-type active region along the second direction is greater than a height of the second p-type active region along the second direction.
8. The semiconductor structure of claim 6 , wherein each of the first n-type active region and the second n-type active region comprises a plurality of fin structure, and a number of the fin structures of the first n-type active region is greater than a number of the fin structures of the second n-type active region.
9. The semiconductor structure of claim 7 , wherein each of the first p-type active region and the second p-type active region comprises a plurality of fin structure, and a number of the fin structures of the first p-type active region is greater than a number of the fin structures of the second p-type active region.
10. A semiconductor standard cell structure, comprising:
an n-type active region and a p-type active region side by side disposed along a first direction; and
a plurality of gate strips extending from a bottom to a top of the semiconductor standard cell structure along a second direction perpendicular to the first direction;
wherein within the semiconductor standard cell structure, each of the gate strips passes over only one of the n-type active region or the p-type active region from a top view.
11. The semiconductor standard cell structure of claim 10 , wherein a height of the n-type active region along the second direction is substantially different from a height of the p-type active region along the second direction.
12. The semiconductor standard cell structure of claim 11 , wherein a width of the n-type active region along the first direction is substantially the same as a width of the p-type active region along the first direction.
13. The semiconductor standard cell structure of claim 12 , wherein a distance between a lower boundary of the n-type active region and a lower boundary of the semiconductor standard cell structure is substantially the same as a distance between a lower boundary of the p-type active region and the lower boundary of the semiconductor standard cell structure.
14. The semiconductor standard cell structure of claim 11 , further comprising a reserved region for metal routing, and the reserved region is free from overlapping the n-type active region and the p-type active region.
15. The semiconductor standard cell structure of claim 14 , wherein a height of the reserved region depends on a number of gate strips of the semiconductor standard cell structure.
16. The semiconductor standard cell structure of claim 10 , wherein the semiconductor standard cell structure includes a negative-AND or a transmission gate.
17. The semiconductor standard cell structure of claim 11 , wherein the n-type active region comprises a plurality of first fin structures thereon along the first direction, and the p-type active region comprises a plurality of second fin structures thereon along the first direction, and a number of the first fin structures is different from a number of the second fin structures.
18. A semiconductor structure, comprising:
a first standard cell including:
an n-type active region and a p-type active region side by side disposed along a first direction; and
a plurality of gate strips extending from a bottom to a top of the first standard cell along a second direction perpendicular to the first direction, wherein within the first standard cell, each of the gate strips passes over only one of the n-type active region or the p-type active region of the first standard cell from a top view; and
a second standard cell including:
an n-type active region and a p-type active region side by side disposed along the first direction; and
a plurality of gate strips extending from a bottom to a top of the second standard cell along the second direction, wherein within the second standard cell, each of the gate strips passes over only one of the n-type active region or the p-type active region of the second standard cell from the top view;
wherein a number of the gate strips in the first standard cell is substantially the same as a number of the gate strips in the second standard cell.
19. The semiconductor structure of claim 18 , each of the first standard cell and the second standard cell further including a reserved region for metal routing, and a height of the reserved region of the first standard cell is the same as a height of the reserved region of the second standard cell.
20. The semiconductor structure of claim 18 , wherein a height of the n-type active region is different from a height of the p-type active region.