Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end
Artificial synaptic devices with a HfO 2 -based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO 2 -based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO 2 -based material. A FET device formed by the present techniques is also provided.
1. A field-effect transistor (FET) device, comprising:
a substrate comprising a first active area separated from a second active area by a shallow trench isolation (STI) region;
at least one ferroelectric FET (FeFET) on the substrate in the first active area having a ferroelectric material comprising a hafnium oxide (HfO 2 )-based material; and
at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric comprising the HfO 2 -based material, and wherein the at least one logic FET further comprises:
the gate dielectric disposed on the substrate;
a dielectric capping layer disposed on the gate dielectric;
a gate metal layer disposed on the dielectric capping layer;
a gate capping layer disposed on the gate metal layer; and
an additional gate metal layer disposed on the gate capping layer.
2. The FET device of claim 1 , wherein the HfO 2 -based material is selected from the group consisting of: pure HfO 2 , Hf ˜0.5 Zr ˜0.5 O 2 , doped HfO 2 , and combinations thereof.
3. The FET device of claim 2 , wherein the doped HfO 2 comprises a dopant selected from the group consisting of: nitrogen (N), carbon (C), silicon (Si), aluminum (Al), lanthanum (La), gadolinium (Gd), yttrium (Y), scandium (Sc), strontium (Sr), and combinations thereof.
4. The FET device of claim 1 , wherein the at least one FeFET further comprises:
the ferroelectric material disposed on the substrate;
a dielectric capping layer disposed on the ferroelectric material; and
an electrode disposed on the dielectric capping layer.
5. The FET device of claim 4 , wherein the dielectric capping layer comprises a material selected from the group consisting of: lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), and combinations thereof.
6. The FET device of claim 4 , wherein the electrode comprises a metal selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), and combinations thereof.
7. The FET device of claim 1 , wherein the dielectric capping layer comprises a material selected from the group consisting of: La 2 O 3 , Al 2 O 3 and combinations thereof.
8. The FET device of claim 1 , wherein the gate capping layer comprises a material selected from the group consisting of: La 2 O 3 , Al 2 O 3 and combinations thereof.
9. The FET device of claim 1 , wherein the gate metal layer and the additional gate metal each comprises a metal selected from the group consisting of: TiN, TaN, and combinations thereof.
10. The FET device of claim 1 , wherein the gate dielectric is selected from the group consisting of: pure HfO 2 , Hf ˜0.5 Zr ˜0.5 O 2 , doped HfO 2 , and combinations thereof.
11. The FET device of claim 10 , wherein the doped HfO 2 comprises a dopant selected from the group consisting of: N, C, Si, Al, La, Gd, Y, Sc, Sr, and combinations thereof.
12. A FET device, comprising:
a substrate comprising a first active area separated from a second active area by a STI region;
at least one FeFET on the substrate in the first active area having a ferroelectric material comprising a HfO 2 -based material selected from the group consisting of: pure HfO 2 , Hf ˜0.5 Zr ˜0.5 O 2 , doped HfO 2 , and combinations thereof; and
at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric comprising the HfO 2 -based material, and wherein the at least one logic FET further comprises:
the gate dielectric disposed on the substrate;
a dielectric capping layer disposed on the gate dielectric;
a gate metal layer disposed on the dielectric capping layer;
a gate capping layer disposed on the gate metal layer; and
an additional gate metal layer disposed on the gate capping layer.
13. The FET device of claim 12 , wherein the doped HfO 2 comprises a dopant selected from the group consisting of: N, C, Si, Al, La, Gd, Y, Sc, Sr, and combinations thereof.
14. The FET device of claim 12 , wherein the at least one FeFET further comprises:
the ferroelectric material disposed on the substrate;
a dielectric capping layer disposed on the ferroelectric material; and
an electrode disposed on the dielectric capping layer.
15. The FET device of claim 14 , wherein the dielectric capping layer comprises a material selected from the group consisting of: La 2 O 3 , Al 2 O 3 , and combinations thereof.
16. The FET device of claim 14 , wherein the electrode comprises a metal selected from the group consisting of: TiN, TaN, and combinations thereof.
17. The FET device of claim 12 , wherein the dielectric capping layer and the gate capping layer each comprises a material selected from the group consisting of: La 2 O 3 , Al 2 O 3 and combinations thereof.
18. The FET device of claim 12 , wherein the gate metal layer and the additional gate metal each comprises a metal selected from the group consisting of: TiN, TaN, and combinations thereof.