Vector store instruction having instruction-specified byte count to be stored supporting big and little endian processing

1. A method for storing vector data in memory with a processor, the method comprising:

obtaining, by the processor, a variable-length vector store instruction that comprises (i) an SX field, (ii) an S field, (iii) an RA field specifying a general purpose register address specification for a memory address, (iv) an RB field specifying a length of the general purpose register address specification, and (v) one or more fields identifying the variable-length vector store instruction, wherein at least two ranges of vector registers for a source are available, wherein each of the at least two ranges of vector registers for the source is controlled by a respective one or more bits in a machine state register;

selecting one of the at least two ranges of vector registers for a target, based on the SX field within the variable-length vector store instruction;

selecting a vector register for the target within the selected range of vector registers for the target, based on the S field within the variable-length vector store instruction;

determining whether data should be stored into memory using big endian byte-ordering or little endian byte-ordering; and

storing data from the vector register into memory by:

iteratively storing data for each of a plurality of bytes in the variable-length vector store instruction into a memory address, wherein each iteration of a storing data comprises:

placing a byte of the plurality of bytes in the memory address according to big endian byte-ordering or little endian byte-ordering; and

selecting a next byte of the plurality of bytes in the variable-length vector store instruction to store into a next memory address.

2. The method of claim 1 , wherein data is stored in leftmost bytes responsive to a determined first byte-ordering, and data is stored in rightmost bytes responsive to a determined second byte ordering.

3. The method of claim 1 , wherein if the length is greater than or equal to a length of the vector register, storing the entire contents of the vector register into memory.

4. The method of claim 1 , wherein if it is determined data should be stored into memory using big endian byte-ordering, further comprising:

storing leftmost data from the vector register into memory.

5. The method of claim 1 , wherein the length is specified in a portion of the bits in the general purpose register.

6. A computer program product, comprising:

a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured to perform an operation for storing vector data in memory with a processor, the operation comprising:

obtaining, by the processor, a variable-length vector store instruction that comprises (i) an SX field, (ii) an S field, (iii) an RA field specifying a general purpose register address specification for a memory address, (iv) an RB field specifying a length of the general purpose register address specification, and (v) one or more fields identifying the variable-length vector store instruction, wherein at least two ranges of vector registers for a source are available, wherein each of the at least two ranges of vector registers for the source is controlled by a respective one or more bits in a machine state register;

selecting one of the at least two ranges of vector registers for a target, based on the SX field within the variable-length vector store instruction;

selecting a vector register for the target within the selected range of vector registers for the target, based on the S field within the variable-length vector store instruction;

determining whether data should be stored into memory using big endian byte-ordering or little endian byte-ordering; and

storing data from the vector register into memory by:

iteratively storing data for each of a plurality of bytes in the variable-length vector store instruction into a memory address, wherein each iteration of a storing data comprises:

placing a byte of the plurality of bytes in the memory address according to big endian byte-ordering or little endian byte-ordering; and

selecting a next byte of the plurality of bytes in the variable-length vector store instruction to store into a next memory address.

7. The computer program product of claim 6 , wherein data is stored in leftmost bytes responsive to a determined first byte-ordering, and data is stored in rightmost bytes responsive to a determined second byte ordering.

8. The computer program product of claim 6 , wherein if the length is greater than or equal to a length of the vector register, storing the entire contents of the vector register into memory.

9. The computer program product of claim 6 , wherein if it is determined data should be stored into memory using big endian byte-ordering, further comprising:

storing leftmost data from the vector register into memory.

10. The computer program product of claim 6 , wherein the length is specified in a portion of the bits in the general purpose register.

11. A system, comprising:

a processor; and

a memory storing a program, which, when executed on the processor, performs an operation for storing a vector, the operation comprising:

obtaining, by the processor, a variable-length vector store instruction that comprises (i) an SX field, (ii) an S field, (iii) an RA field specifying a general purpose register address specification for a memory address, (iv) an RB field specifying a length of the general purpose register address specification, and (v) one or more fields identifying the variable-length vector store instruction, wherein at least two ranges of vector registers for a source are available, wherein each of the at least two ranges of vector registers for the source is controlled by a respective one or more bits in a machine state register;

selecting one of the at least two ranges of vector registers for a target, based on the SX field within the variable-length vector store instruction;

selecting a vector register for the target within the selected range of vector registers for the target, based on the S field within the variable-length vector store instruction;

determining whether data should be stored into memory using big endian byte-ordering or little endian byte-ordering; and

storing data from the vector register into memory by:

iteratively storing data for each of a plurality of bytes in the variable-length vector store instruction into a memory address, wherein each iteration of a storing data comprises:

placing a byte of the plurality of bytes in the memory address according to big endian byte-ordering or little endian byte-ordering; and

selecting a next byte of the plurality of bytes in the variable-length vector store instruction to store into a next memory address.

12. The system of claim 11 , wherein data is stored in leftmost bytes responsive to a determined first byte-ordering, and data is stored in rightmost bytes responsive to a determined second byte ordering.

13. The system of claim 11 , wherein if the length is greater than or equal to a length of the vector register, storing the entire contents of the vector register into memory.

14. The system of claim 11 , wherein if it is determined data should be stored into memory using big endian byte-ordering, further comprising:

storing leftmost data from the vector register into memory.

15. The system of claim 11 , wherein the length is specified in a portion of the bits in the general purpose register.