Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration

1. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing an encapsulant around the first semiconductor die;

forming thin-film interconnect structure including a plurality of insulating layers over the first semiconductor die and encapsulant;

forming a conductive via through the plurality of insulating layers and extending from a top surface of the thin-film interconnect structure to a bottom surface of the thin-film interconnect structure, wherein the conductive via physically contacts an active surface of the first semiconductor die;

providing a second semiconductor die including a first interconnect structure formed over an active surface of the second semiconductor die; and

disposing the second semiconductor die over the first semiconductor die with the conductive via extending to the first interconnect structure.

2. The method of claim 1 , wherein the conductive via extends in a linear path directly from the active surface of the first semiconductor die to the first interconnect structure of the second semiconductor die.

3. The method of claim 1 , wherein forming the thin-film interconnect structure and conductive via includes:

forming a first insulating layer of the plurality of insulating layers including an opening in the first insulating layer exposing the active surface of the first semiconductor die;

forming a first conductive layer including a first portion of the first conductive layer in the opening of the first insulating layer;

forming a second insulating layer of the plurality of insulating layers including an opening in the second insulating layer aligned with the opening in the first insulating layer; and

forming a second conductive layer including a first portion of the second conductive layer in the opening of the second insulating layer on the first portion of the first insulating layer.

4. The method of claim 3 , further including forming a second portion of the first conductive layer extending from the active surface of the first semiconductor die within a footprint of the second semiconductor die to outside a footprint of the second semiconductor die.

5. The method of claim 4 , further including disposing a conductive bump over the second portion of the first conductive layer outside the footprint of the second semiconductor die.

6. The method of claim 4 , further including:

forming a second portion of the second conductive layer on the second portion of the first conductive layer; and

disposing the second semiconductor die over the first semiconductor die with the second portion of the second conductive layer in contact with a second interconnect structure of the second semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing an encapsulant over the first semiconductor die;

forming a thin-film interconnect structure over the first semiconductor die and encapsulant, wherein the thin-film interconnect structure includes a conductive via extending from a top surface of the thin-film interconnect structure to a bottom surface of the thin-film interconnect structure;

providing a second semiconductor die including an interconnect structure formed over the second semiconductor die; and

disposing the second semiconductor die over the first semiconductor die with the conductive via extending to the interconnect structure of the second semiconductor die.

8. The method of claim 7 , wherein forming the thin-film interconnect structure includes:

forming a first insulating layer on the encapsulant and first semiconductor die;

forming a second insulating layer over the first insulating layer; and

forming the conductive via extending through the first insulating layer and the second insulating layer.

9. The method of claim 7 , wherein the conductive via extends in a vertical linear path from the first semiconductor die to the interconnect structure of the second semiconductor die.

10. The method of claim 7 , further including forming the thin-film interconnect structure to include a conductive trace, wherein the conductive trace extends from within a footprint of the second semiconductor die to outside a footprint of the second semiconductor die.

11. The method of claim 7 , wherein a first surface of the encapsulant is coplanar with a first surface of the first semiconductor die.

12. The method of claim 11 , wherein a second surface of the encapsulant is coplanar with a second surface of the first semiconductor die opposite the first surface of the first semiconductor die.

13. The method of claim 7 , wherein the conductive via provides an electrical conduction path length between the first semiconductor die and second semiconductor die of less than 300 microns.

14. The method of claim 7 , wherein the conductive via provides an electrical conduction path length between the first semiconductor die and second semiconductor die of less than 100 microns.

15. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing an encapsulant around the first semiconductor die;

forming a thin-film interconnect structure over the first semiconductor die and encapsulant, wherein the thin-film interconnect structure includes a conductive via extending from a top surface of the thin-film interconnect structure to a bottom surface of the thin-film interconnect structure; and

disposing a second semiconductor die over the first semiconductor die with the conductive via providing vertical drop-down electrical routing from the first semiconductor die to the second semiconductor die.

16. The method of claim 15 , further including disposing a conductive bump over the encapsulant and electrically connected to the first semiconductor die and second semiconductor die.

17. The method of claim 15 , further including:

providing the second semiconductor die to include an interconnect structure formed on the second semiconductor die; and

disposing the second semiconductor die with the conductive via in direct physical contact with the interconnect structure and an active surface of the first semiconductor die.

18. The method of claim 15 , wherein the conductive via provides an electrical conduction path length between the first semiconductor die and second semiconductor die of less than 100 microns.

19. A semiconductor device, comprising:

a first semiconductor die;

an encapsulant deposited around the first semiconductor die;

a thin-film interconnect structure formed over the first semiconductor die and encapsulant, wherein the thin-film interconnect structure includes an insulating layer and a conductive via formed in physical contact with a contact pad of the first semiconductor die and extending vertically from a top surface of the thin-film interconnect structure through the insulating layer and to a bottom surface of the thin-film interconnect structure; and

a second semiconductor die disposed over the first semiconductor die with an interconnect structure of the second semiconductor die in physical contact with the conductive via.

20. The semiconductor device of claim 19 , wherein the conductive via provides an electrical conduction path length between the first semiconductor die and second semiconductor die of less than 100 microns.

21. The semiconductor device of claim 19 , wherein a surface of the encapsulant is coplanar with a surface of the first semiconductor die.

22. The semiconductor device of claim 19 , further including a conductive bump disposed on the thin-film interconnect structure over the encapsulant and electrically connected to the first semiconductor die and second semiconductor die.