IP Library › Granted Patent US 10,693,012

Granted Patent B2

US 10,693,012 · App. 15/081,251 · Granted Jun 23, 2020

Semiconductor device and method for manufacturing the same

Inventor: Yoshinobu Asami (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L29/7869 H01L21/0262 H01L21/02063 H01L21/02554 H01L21/02565 H01L21/02631 H01L21/31155 H01L21/465 H01L21/469 H01L27/1207 H01L29/42384 H01L29/66969 H01L29/78603 H01L29/78648 H01L29/78696

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Quick Facts

Patent No.: US 10,693,012
App. No.: 15/081,251
Granted: Jun 23, 2020
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

Claims (77)

1. A semiconductor device comprising:

a first insulating layer over a substrate;

a first oxide insulator over the first insulating layer;

an oxide semiconductor over the first oxide insulator;

a second oxide insulator over the oxide semiconductor;

a gate insulating layer over the second oxide insulator;

a gate electrode layer over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor; and

a second insulating layer over the first insulating layer,

wherein each of the first oxide insulator and the second oxide insulator comprises indium, an element M, and zinc,

wherein the element M is gallium, aluminum, titanium, yttrium, or tin,

wherein the oxide semiconductor comprises a first region, a second region, a third region, a fourth region, and a fifth region,

wherein the first region overlaps with the source electrode layer,

wherein the second region overlaps with the drain electrode layer,

wherein the third region overlaps with the gate electrode layer,

wherein the fourth region is in contact with the first region and the third region,

wherein the fifth region is in contact with the second region and the third region,

wherein an atomic ratio of an element N in each of the fourth region and the fifth region is higher than in each of the first region and the second region,

wherein the element N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon,

wherein the second insulating layer is in contact with an entire side surface of the first oxide insulator and an entire side surface of the oxide semiconductor which are parallel to a channel width direction, and

wherein the second insulating layer does not include a region having a level higher than a top surface of the source electrode layer or a top surface of the drain electrode layer.

2. The semiconductor device according to claim 1 ,

wherein each of the fourth region and the fifth region has a lower resistance than the third region.

3. The semiconductor device according to claim 1 ,

wherein a top surface of the gate insulating layer over the fourth region or the fifth region is positioned at a lower level than the top surface of the source electrode layer or the drain electrode layer.

4. The semiconductor device according to claim 1 ,

wherein each of the first region and the second region has a lower resistance than the third region.

5. The semiconductor device according to claim 1 , further comprising a bottom gate under the oxide semiconductor,

wherein the bottom gate overlaps with the oxide semiconductor.

6. The semiconductor device according to claim 1 ,

wherein the element N is added by an ion implantation method.

7. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor comprises indium and gallium.

8. The semiconductor device according to claim 1 ,

wherein a thickness of the entire fourth region is smaller than a thickness of the first region, and

wherein a thickness of the entire fifth region is smaller than a thickness of the second region.

9. A semiconductor device comprising:

a first insulating layer over a substrate;

a first oxide insulator over the first insulating layer;

an oxide semiconductor over the first oxide insulator;

a second oxide insulator over the oxide semiconductor;

a gate insulating layer over the second oxide insulator;

a gate electrode layer over the gate insulating layer; and

a source electrode layer and a drain electrode layer over the oxide semiconductor,

wherein each of the first oxide insulator, the oxide semiconductor and the second oxide insulator comprises indium and zinc,