Circuit and method for digital-to-analog conversion using three-level cells

1. A circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, negative electricity or floating, the circuit comprising:

a preprocess circuit configured to receive thermometer code data generated from signed binary data and generate, from the thermometer code data, a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM); and

a shift circuit configured to store the cell pointer and shift the cell pointer according to the shift count, wherein

the cell pointer is shifted in proportion to an absolute value of the signed binary data in a direction depending on a sign of the signed binary data.

2. The circuit of claim 1 , wherein:

a value represented by the signed binary data identifies a number of “1's” within the thermometer code data,

the shift circuit is configured to shift the cell pointer according to the number of “1's” within in the shift count, and

the preprocess circuit is configured to generate the shift count from upper half bits of the thermometer code data when the signed binary data is positive and from lower half bits of the thermometer code data when the signed binary data is negative.

3. The circuit of claim 1 , wherein:

the preprocess circuit is configured to generate cell code data from the thermometer code data, and

the shift circuit is configured to generate cell control data, which is provided to the plurality of 3-level cells, by shifting the cell code data according to the cell pointer.

4. The circuit of claim 3 , wherein:

the preprocess circuit is configured to generate the cell code data comprising first code data, second code data, or third code data, and

each of the plurality of 3-level cells provides the positive electricity according to the first code data, provides the negative electricity according to the second code data, and provides the floating according to the third code data.

5. The circuit of claim 4 , wherein the preprocess circuit is configured to generate the first code data using upper half bits of the thermometer code data.

6. The circuit of claim 4 , wherein the preprocess circuit is configured to generate the second code data by inverting lower half bits of the thermometer code data.

7. The circuit of claim 4 , wherein the preprocess circuit is configured to generate the third code data by inverting upper half bits of the thermometer code data when the signed binary data is positive and generate the third code data using lower half bits of the thermometer code data when the signed binary data is zero or negative.

8. The circuit of claim 3 , further comprising:

an analog generator comprising the plurality of 3-level cells and a summing circuit that sums electricity provided by the plurality of 3-level cells, wherein

the plurality of 3-level cells are configured to supply current to the summing circuit using the positive electricity, withdraw current from the summing circuit using the negative electricity, or float a terminal connected to the summing circuit according to the cell control data.

9. A circuit for digital-to-analog conversion using m 3-level cells mutually independently providing positive electricity, negative electricity or floating, where the m is an integer greater than 1, the circuit comprising:

a preprocess circuit comprising a first logic circuit configured to output a shift count for shifting a cell pointer pointing to one of the m 3-level cells for dynamic element matching (DEM) by performing a bitwise operation on thermometer code data, which is 2m bits, generated from signed binary data; and

a shift circuit comprising a latch that stores the cell pointer and a first shifter configured to shift the cell pointer stored in the latch according to the shift count, wherein

an output of the first shifter coincides with the cell pointer stored in the latch being shifted in proportion to an absolute value of the signed binary data in a direction depending on a sign of the signed binary data.

10. The circuit of claim 9 , wherein:

a value represented by the signed binary data identifies a number of “1's” within the thermometer code data,

the first shifter is configured to shift the cell pointer according to the number of “1's” within the shift count, and

the first logic circuit is configured to output upper m-bits of the thermometer code data when a least significant bit of the upper m-bits of the thermometer code data is “1” and outputs lower m-bits of the thermometer code data when the least significant bit is “0”.

11. The circuit of claim 9 , wherein:

the preprocess circuit further comprises a second logic circuit configured to generate cell code data by performing a bitwise operation on the thermometer code data, and

the shift circuit further comprises a second shifter configured to output cell control data, which is provided to the m 3-level cells, by shifting the cell code data according to the cell pointer stored in the latch.

12. The circuit of claim 11 , wherein:

the second logic circuit is configured to generate the cell code data comprising at least one of m-bit first code data, m-bit second code data, and m-bit third code data, and

each of the m 3-level cells provides the positive electricity according to the first code data, provides the negative electricity according to the second code data, and provides the floating according to the third code data.

13. The circuit of claim 12 , wherein the second logic circuit is configured to output upper m-bits of the thermometer code data as the first code data.

14. The circuit of claim 12 , wherein the second logic circuit is configured to output the second code data by inverting lower m-bits of the thermometer code data.

15. The circuit of claim 12 , wherein the second logic circuit is configured to output the third code data by inverting upper m-bits of the thermometer code data when a least significant bit of the upper m-bits of the thermometer code data is “1” and output lower m-bits of the thermometer code data as the third code data when the least significant bit is “0”.

16. The circuit of claim 12 , further comprising:

an analog generator comprising the m 3-level cells and a summing circuit that sums electricity provided by the m 3-level cells, wherein

the m 3-level cells are configured to supply current to the summing circuit using the positive electricity, withdraw current from the summing circuit using the negative electricity, or float a terminal connected to the summing circuit according to the cell control data.

17. A method for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, negative electricity or floating, the method comprising:

receiving thermometer code data generated from signed binary data;

generating, from the thermometer code data, a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM); and

shifting the cell pointer according to the shift count and storing the cell pointer, wherein

the cell pointer is shifted in proportion to an absolute value of the signed binary data in a direction depending on a sign of the signed binary data.

18. The method of claim 17 , wherein:

a value represented by the signed binary data identifies a number of “1's” within the thermometer code data,

the shifting comprises shifting the cell pointer according to the number of “1's” within the shift count, and

the generating of the shift count comprises generating the shift count from upper half bits of the thermometer code data when the signed binary data is positive and from lower half bits of the thermometer code data when the signed binary data is negative.

19. The method of claim 17 , further comprising:

generating cell code data from the thermometer code data; and

before the shifting of the cell pointer, generating cell control data, which is provided to the plurality of 3-level cells, by shifting the cell code data according to the cell pointer.

20. The method of claim 19 , further comprising generating an analog signal by summing the positive electricity, the negative electricity, and the floating provided by the plurality of 3-level cells according to the cell control data.