Multi-wire permuted forward error correction

1. An apparatus comprising:

a plurality of forward error-correction (FEC) encoders configured to generate a plurality of streams of FEC-encoded bits, each FEC encoder configured to receive a respective subset of a plurality of subsets of information bits, and to responsively generate a corresponding stream of FEC-encoded bits of the plurality of streams of FEC-encoded bits; and

a permuter configured to receive the plurality of streams of FEC-encoded bits, and to responsively provide each stream of FEC-encoded bits of the plurality of streams of FEC-encoded bits to a respective sub-channel encoder of a plurality of sub-channel encoders, wherein the permuter is configured to provide sequential streams of FEC-encoded bits received from a given FEC encoder in a cyclically varying order to each sub-channel encoder of the plurality of sub-channel encoders; and

the plurality of sub-channel encoders configured to generate a set of codewords of a vector signaling code for transmission over a multi-wire bus, each codeword of the set of codewords generated by summing a plurality of weighted sub-channel vectors, each weighted sub-channel vector generated by a respective sub-channel encoder modulating a corresponding sub-channel vector of a plurality of mutually orthogonal sub-channel vectors according to a bit in the received stream of FEC-encoded bits.

2. The apparatus of claim 1 , wherein each stream of FEC encoded bits corresponds to a multi-bit packet.

3. The apparatus of claim 1 , wherein each stream of FEC encoded bits corresponds to a single bit.

4. The apparatus of claim 1 , wherein the permuter comprises a plurality of multiplexors, each multiplexor associated with a corresponding sub-channel encoder and configured to receive all of the streams of FEC encoded bits and to selectively provide the stream of FEC encoded bits to the respective sub-channel encoder.

5. The apparatus of claim 1 , wherein the permuter comprises a plurality of de-multiplexors, each de-multiplexor associated with a corresponding FEC encoder and configured to receive a corresponding stream of FEC encoded bits from the corresponding FEC encoder and to selectively provide the received stream of FEC encoded bits to the respective sub-channel encoder.

6. The apparatus of claim 1 , wherein the permuter comprises a plurality of buffers configured to buffer the plurality of streams of FEC encoded bits prior to providing the plurality of streams of FEC encoded bits to the plurality of sub-channel encoders.

7. The apparatus of claim 1 , wherein the sub-channel encoders are ENRZ sub-channel encoders.

8. The apparatus of claim 1 , wherein the permuter further comprises a counter configured to provide a plurality of count signals staggered in time, the staggered count signals used for sequentially providing sequential streams of FEC-encoded bits to each sub-channel encoder in the cyclically varying order.

9. The apparatus of claim 1 , wherein each stream of FEC encoded bits is integrated prior to being provided to the respective sub-channel encoder.

10. A method comprising:

obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits;

generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits;

providing each stream of FEC-encoded bits of the plurality of streams of FEC-encoded bits to a respective sub-channel encoder of a plurality of sub-channel encoders, wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided in a cyclically varying order to each sub-channel encoder of the plurality of sub-channel encoders;

generating a set of codewords of a vector signaling code, each codeword of the set of codewords generated by summing a plurality of weighted sub-channel vectors, each weighted sub-channel vector generated by a respective sub-channel encoder modulating a corresponding sub-channel vector of a plurality of mutually orthogonal sub-channel vectors according to a bit in the received stream of FEC-encoded bits; and

transmitting the set of codewords of the vector signaling code over a multi-wire bus.

11. The method of claim 10 , wherein each stream of FEC encoded bits corresponds to a multi-bit packet.

12. The method of claim 10 , wherein each stream of FEC encoded bits corresponds to a single bit.

13. The method of claim 10 , wherein providing each stream of FEC-encoded bits comprises selectively providing the stream of FEC encoded bits to the respective sub-channel encoder using a corresponding multiplexor of a plurality of multiplexors, each multiplexor receiving all of the streams of FEC encoded bits and associated with a corresponding sub-channel encoder.

14. The method of claim 10 , wherein providing each stream of FEC-encoded bits comprises selectively providing the received stream of FEC encoded bits to the respective sub-channel encoder via a de-multiplexor of a plurality of de-multiplexors, each de-multiplexor associated with a corresponding FEC encoder.

15. The method of claim 10 , further comprising buffering the plurality of streams of FEC encoded bits prior to providing the plurality of streams of FEC encoded bits to the plurality of sub-channel encoders.

16. The method of claim 10 , wherein the sub-channel encoders are ENRZ sub-channel encoders.

17. The method of claim 10 , wherein sequential streams of FEC-encoded bits are provided to corresponding sub-channel encoders in the cyclically varying order according to respective count signals of a plurality of count signals, the plurality of count signals being staggered in time.

18. The method of claim 10 , wherein each stream of FEC encoded bits is integrated prior to being provided to the respective sub-channel encoder.