MEMS cavity with non-contaminating seal
A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
1. A semiconductor device comprising:
a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers;
a piezoelectric material layer between the second silicon layer and the third silicon layer;
a cavity within the first silicon layer bounded by interior surfaces of the second and third silicon layers, wherein a microelectromechanical system (MEMS) resonator is disposed within the cavity;
a passageway through the second silicon layer to enable removal of oxide from within the cavity during cavity formation, the passageway having at least one bend to prevent line-of-sight view through the second silicon layer into the cavity;
a via which extends through the second silicon layer to provide electrical impetus to excite the piezoelectric material layer; and
a metal feature disposed within the passageway to hermetically seal the cavity, wherein the metal feature and the via are formed from a common metal material deposited via a common deposition process.
2. The semiconductor device of claim 1 wherein the semiconductor device comprises a doped single-crystal silicon layer and a doped polycrystalline silicon layer separated from one another by the piezoelectric material layer.
3. The semiconductor device of claim 1 wherein the interior surface of the second silicon layer is disposed adjacent the first oxide layer and the passageway extends from the interior surface of the second silicon layer toward an exterior surface of the second silicon layer opposite the interior surface of the second silicon layer, and wherein the metal feature extends over the exterior surface around and into the passageway to hermetically seal the passageway.
4. The semiconductor device of claim 1 wherein the piezoelectric material layer comprises aluminum nitride.
5. The semiconductor device of claim 1 wherein the common deposition process comprises a metal sputtering process.
6. The semiconductor device of claim 1 wherein the passageway is pattered so as to provide a cross-sectional dimension of less than two microns and a depth-to-width ratio relative to a surface of the second silicon layer of greater than five.
7. The semiconductor device of claim 1 wherein the semiconductor device further comprises an electrode conductively coupled to the metal feature to provide a fixed-potential connection to the metal feature.
8. A method of fabricating a semiconductor device, the method comprising:
forming a material stack comprising a microelectromechanical system (MEMS) resonator, the material stack having (i) a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers and (ii) an oxide-filled trench extending through the first silicon layer from the first oxide layer to the second oxide layer and (iii) a spezoelectric material layer between the second silicon layer and the third silicon layer and (iv) a cavity within the first silicon layer bounded by interior surfaces of the second and third silicon layers, wherein the MEMS resonator is disposed within the cavity;
forming one or more passageways that extend through the second silicon layer to the first oxide layer, the one or more passageways being formed so as to provide at least one bend to prevent line-of-sight view through the second silicon layer into the cavity;
forming a via which extends through the second silicon layer to provide electrical impetus to excite the piezoelectric material layer;
wherein the method further comprises removing oxide from the oxide-filled trench and regions of the first and second oxide layers through the one or more passageways and sealing the one or more passageways with a metal feature after removing oxide from the oxide-filled trench and regions of the first and second oxide layers; and
wherein the metal feature and the via are formed from a common metal material deposited via a common deposition process.
9. The method of claim 8 wherein forming the material stack having the oxide-filled trench that extends through the first silicon layer comprises etching a trench through the first silicon layer to define the MEMS resonator and disposing oxide within the trench, and wherein removing oxide from the oxide-filled trench and regions of the first and second oxide layer comprises removing oxide from regions adjacent the MEMS resonator to form the cavity, such that the MEMS resonator is free to move within the cavity.
10. The method of claim 8 wherein sealing the one or more passageways with metal feature comprises disposing the common metal material over a surface of the second silicon layer over openings of the one or more passageways via a sputtering process.
11. A semiconductor device comprising:
a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers;
a piezoelectric material layer between the second silicon layer and the third silicon layer;
a cavity within the first silicon layer bounded by interior surfaces of the second and third silicon layers, wherein a microelectromechanical system (MEMS) resonator is disposed within the cavity;
a vent that extends at least through the second silicon layer to enable material removal from within the cavity during cavity formation, the vent including first and second interconnected passageways having non-parallel axes;
a via which extends through the second silicon layer to provide electrical impetus to excite the piezoelectric material layer; and
a sealant material disposed within the second passageway to hermetically seal the cavity, wherein the sealant material and the via are formed from a common metal material deposited via a common deposition process.
12. The semiconductor device of claim 11 wherein the vent comprises a third passageway that extends from the second passageway to the cavity, in a direction orthogonal to the axis of the second passageway.
13. The semiconductor device of claim 11 wherein the vent comprises a third passageway interconnected to the first passageway by the second passageway, the third passageway extending in a direction non-coaxial to, and parallel to, the axis of the first passageway.
14. The semiconductor device of claim 11 wherein the non-parallel axes are perpendicular.
15. The semiconductor device of claim 11 wherein the piezoelectric material layer comprises aluminum nitride.
16. The semiconductor device of claim 11 wherein the common deposition process comprises a metal sputtering process.
17. The semiconductor device of claim 11 wherein the vent is pattered so as to provide a cross-sectional dimension of less than two microns and a depth-to-width ratio relative to a surface of the second silicon layer of greater than five.
18. The semiconductor device of claim 11 wherein the sealant material forms a metal feature and wherein the semiconductor device further comprises an electrode conductively coupled to the metal feature to provide a fixed-potential connection to the metal feature.
19. A method of fabricating a semiconductor device, the method comprising:
forming a material stack comprising a microelectromechanical system (MEMS) resonator, the material stack having (i) a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers and (ii) an oxide-filled trench extending through the first silicon layer from the first oxide layer to the second oxide layer and (iii) a piezoelectric material layer between the second silicon layer and the third silicon layer and (iv) a cavity within the first silicon layer bounded by interior surfaces of the second and third silicon layers, wherein the MEMS resonator is disposed within the cavity;
forming a vent that extends through at least the second silicon layer to the first oxide layer and that includes first and second interconnected passageways in which the second passageway is substantially narrower than the first passageway, the first and second interconnected passageways being formed so as to provide at least one bend to prevent line-of-sight view through the second silicon layer into the cavity;
forming a via which extends through the second silicon layer to provide electrical impetus to excite the piezoelectric material layer;
wherein the method further comprises removing oxide from the oxide-filled trench and regions of the first and second oxide layers through the first and second passageways of the vent to form a cavity between the second and third silicon layers, and disposing a sealant material within the second passageway to hermetically seal the cavity; and
wherein the sealant material and the via are formed from a common metal material deposited via a common deposition process.
20. The method of claim 19 wherein forming the vent comprises:
forming a third passageway that extends from the second passageway to the cavity; and
routing the second passageway along an axis substantially orthogonal to axes along which the first and third passageways are routed.
21. The method of claim 19 wherein forming the vent comprises:
forming a third passageway that is interconnected to the first passageway by the second passageway; and
routing the first and third passageways along respective axes that are parallel and non-concentric.