IP Library › Granted Patent US 10,699,628
Granted Patent B2
US 10,699,628 · App. 15/596,138 · Granted Jun 30, 2020

Display system and vehicle

Inventors: Shunpei Yamazaki (Tokyo, JP); Takayuki Ikeda (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/2092B60K35/00B60K37/02G09G3/3225G09G3/3275G09G5/14B60K2370/15B60K2370/52G09G2300/0426G09G2300/0814G09G2300/0842G09G2320/068G09G2320/08G09G2330/021G09G2354/00G09G2380/02G09G2380/10
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Quick Facts
Patent No.
US 10,699,628
App. No.
15/596,138
Granted
Jun 30, 2020
Kind
B2
Abstract

An object is to provide a display system with a novel structure and a vehicle. The display system includes a display and a control IC. The control IC includes a frame memory, an arithmetic circuit, and a memory circuit. The display has a curved display surface. The frame memory has a function of holding first image data dedicated to displaying an image on a flat surface. The memory circuit has a function of storing shape data on the display. The arithmetic circuit has a function of converting first coordinates of the curved display surface into second coordinates of the flat surface included in the first image data, by performing arithmetic operation in accordance with the shape data. The arithmetic circuit has a function of outputting the first image data stored in the frame memory to the display as second image data on the basis of the second coordinates.

Claims (31)

1. A display system comprising:

a display comprising a curved display surface; and

a control IC comprising a memory circuit, a reference memory circuit, a first circuit, and a second circuit,

wherein:

the memory circuit is configured to generate a first current corresponding to first analog data, and to generate a second current corresponding to the first analog data and second analog data,

the reference memory circuit is configured to generate a reference current corresponding to reference data,

the first circuit is configured to generate and hold a third current corresponding to a difference between the first current and the reference current when the first current is lower than the reference current,

the second circuit is configured to generate and hold a fourth current corresponding to a difference between the first current and the reference current when the first current is higher than the reference current, and

one of the first circuit and the second circuit is configured to generate a fifth current corresponding to third analog data from the second current and one of the third current and the fourth current.

2. The display system according to claim 1 , further comprising:

a first wiring electrically connected to the first circuit, the second circuit, and the memory circuit; and

a second wiring electrically connected to the reference memory circuit.

3. The display system according to claim 1 , further comprising:

a current source circuit;

a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and the memory circuit; and

a second wiring electrically connected to the current source circuit and the reference memory circuit.

4. The display system according to claim 1 ,

wherein each of the memory circuit and the reference memory circuit comprises a transistor, and

wherein the display system further comprises:

a current source circuit;

a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and one of a source and a drain of the transistor of the memory circuit; and

a second wiring electrically connected to the current source circuit and one of a source and a drain of the transistor of the reference memory circuit.

5. The display system according to claim 1 ,

wherein each of the memory circuit and the reference memory circuit comprises a first transistor, a second transistor, and a capacitor,

wherein the display system further comprises:

a current source circuit;

a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and one of a source and a drain of the first transistor of the memory circuit; and

a second wiring electrically connected to the current source circuit and one of a source and a drain of the first transistor of the reference memory circuit, and

wherein in each of the memory circuit and the reference memory circuit, a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and an electrode of the capacitor.

6. The display system according to claim 1 , further comprising a switch between the first circuit and the second circuit.

7. The display system according to claim 1 , wherein the display system is configured to perform product-sum operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: YAMAZAKI, SHUNPEI; IKEDA, TAKAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 042838/0026 →
Priority Claims (1)
JP 2016-098706 · May 17, 2016 · national
Continuity (1)
Related Publication 20170337867A1 · Nov 23, 2017
Cited By (1)
US 12,475,948