IC wafer for identification of circuit dies after dicing
Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.
1. An integrated circuit (IC) structure having a plurality of circuit dies each bounded by a set of scribe lines, the IC structure comprising:
a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies, wherein the plurality of reference features of the one of the plurality of circuit dies include a first reference line extending along a first axis of the IC structure and a second reference line extending along a second axis orthogonal to the first axis of the IC structure, and
a plurality of identification features each positioned in a second, different layer of the one of the plurality of circuit dies, the plurality of identification features of the one of the plurality of circuit dies having an offset vector indicative of a positional difference between the identification features for the circuit dies and the reference features for the one of the plurality of circuit dies,
wherein one or both of the first reference line and the second reference line of each one of the plurality of circuit dies is equidistant from a respective one of the set of scribe lines for each circuit die of the plurality of circuit dies.
2. The IC structure of claim 1 , wherein the plurality of reference features and the plurality of identification features of each circuit die are included within a functional region of the respective circuit die.
3. The IC structure of claim 1 , wherein the offset vector for each circuit die of the IC structure along a shared axis has a same offset orientation.
4. The IC structure of claim 1 , wherein one or both of the plurality of reference features and the plurality of identification features comprise one of a metal wire or an insulator.
5. The IC structure of claim 1 , wherein an aligned row of circuit dies in the IC structure includes a first circuit die having a first offset vector, and a second circuit die having a second offset vector, wherein an offset distance for the identification features in the second circuit die is twice the offset distance for the identification features in the first circuit die.
6. The IC structure of claim 5 , wherein the aligned row of circuit dies in the IC structure further includes a third circuit die having a third offset vector, wherein an offset distance for the identification features in the third circuit die is three times the offset distance for the identification features in the first circuit die.
7. The IC structure of claim 1 , wherein the plurality of identification features include two identification lines, each parallel to a respective one of the first and the second reference lines of the plurality of reference features.