Apparatuses and methods for detecting a loop count in a delay-locked loop
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.
1. An apparatus comprising:
a divider circuit configured to receive a periodic signal and divide the periodic signal into a first divided signal and a second divided signal, wherein the first divided signal is complimentary to the second divided signal;
a counter circuit configured to determine a first count based on a number of rising edges of the first divided signal, determine a second count based on a number of rising edges of the second divided signal, and provide a third count value which is a sum of the first count and the second count; and
a delay path configured to change a delay value based on the third count.
2. The apparatus of claim 1 , wherein the first count is determined during a first enabled period and the second count is determined during a second enabled period.
3. The apparatus of claim 2 , wherein the first enabled period is produced responsive to the first divided signal and the second enabled period is produced responsive to the second divided signal.
4. The apparatus of claim 2 , wherein the counter circuit includes a first flip-flop configured to receive the first divided signal and produce a first enable signal responsive to the first divided signal and a second flip-flop is configured to receive the second divided signal and produce a second enable signal responsive to the second divided signal,
wherein the first enabled period is produced responsive, at least in part, to the first enable signal and the second enabled period is produced responsive, at least in part, to the second enable signal.
5. The apparatus of claim 4 , wherein the first flip-flop and the second-flip flop are further configured to receive a start signal and a stop signal, wherein the first enable period and the second enable period are produced responsive, at least in part, to the start signal and the stop signal.
6. The apparatus of claim 1 , wherein the counter circuit comprises a loop counter that includes a first ripple counter configured to generate the first count and a second ripple counter configured to generate the second count.
7. The apparatus of claim 1 , wherein the counter circuit comprises a loop counter that includes an adder configured to provide the third count.
8. The apparatus of claim 1 , wherein the third count is a total number of clock cycles that occur during an initialization of a delay-locked loop.
9. A method comprising:
dividing a periodic signal into a first divided signal and a second divided signal complementary to the first divided signal;
counting a number of periods of the first divided signal to produce a first count value;
counting a number of periods of the second divided signal to produce a second count value;
adding the first and second count values to produce a third count value; and
changing a delay value of propagating the periodic signal responsive to the third count value.
10. The method of claim 9 , wherein counting the number of periods of the first divided signal comprises counting a number of rising edges of the first divided signal and counting the number of periods of the second divided signal comprises counting a number of rising edges of the second divided signal.
11. The method of claim 9 , wherein the counting the number of periods of the first divided signal is performed during a first enabled period and the counting the number of periods of the first divided signal is performed during a second enabled period.
12. The method of claim 11 , further comprising receiving a start signal, wherein the first enabled period and the second enabled period begin responsive, at least in part, to the start signal.
13. The method of claim 12 , wherein the first enable period and the second enable period begin further responsive to the first divided signal and the second divided signal, respectively.
14. The method of claim 11 , further comprising receiving a stop signal, wherein the first enabled period and the second enabled period end responsive, at least in part, to the stop signal.
15. The method of claim 9 , wherein the third count value corresponds to a number of clock cycles for a reference clock to traverse a timing loop.
16. An apparatus comprising:
a first counter circuit configured to determine a first count value based on a number of periods of a first periodic signal;
a second counter circuit configured to determine a second count value based on a number of periods of a second periodic signal, wherein the first and second periodic signal are derived from a same periodic signal; and
an adder configured to sum the first count value and the second count value to provide a third count value, wherein the third count value is used to change a delay value of a delay path.
17. The apparatus of claim 16 , wherein the first periodic signal and the second periodic signals are complementary.
18. The apparatus of claim 16 , wherein the first periodic signal and the second periodic signal are divided signals of the same periodic signal.
19. The apparatus of claim 16 , wherein the number of periods of the first periodic signal is determined by a number of rising edges of the first periodic signal.
20. The apparatus of claim 16 , wherein the number of periods of the second periodic signal is determined by a number of rising edges of the second periodic signal.