IP Library › Granted Patent US 10,705,593
Granted Patent B2
US 10,705,593 · App. 16/246,636 · Granted Jul 7, 2020

Method and apparatus for power management

Inventors: Kuchul Jung (Seoul, KR); Kisun Lee (Gyeonggi-do, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F1/3287G06F1/263G06F1/30G06F1/3212G06F11/0757H04B1/1615
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Quick Facts
Patent No.
US 10,705,593
App. No.
16/246,636
Granted
Jul 7, 2020
Kind
B2
Abstract

An apparatus is provided comprising a system including one or more electronic components; a power input unit arranged to supply power to the system; and a power management module configured to: detect whether the system is in an abnormal state, and in response to detecting that the system is in the abnormal state, adjust at least one of (i) power supplied from a battery to the system, (ii) the power supplied from the power input unit to the system, and (iii) power supplied from the power input unit to the battery.

Claims (58)

1. An electronic device comprising:

a touch screen;

a communication circuitry;

a memory;

a battery;

a power input unit;

a watch-dog timer; and

at least one processor configured to:

control the power input unit to supply power to the battery, the touch screen and the communication circuitry in a normal operation state;

control the battery to supply the power to the touch screen and the communication circuitry in an abnormal operation state;

control the watch-dog timer to monitor whether the at least one processor identifies data within a predetermined time;

when the at least one processor does not identity the data within the predetermined time, control the watch-dog timer to determine that the at least one processor is in the abnormal operation state; and

in response to determining that the at least one processor is in the abnormal operation state, control the power input unit to block power supplied to the battery, the touch screen and the communication circuitry.

2. The electronic device of claim 1 , wherein the data comprises a register bit.

3. The electronic device of claim 1 , wherein the at least one processor is further configured to:

when the at least one processor identifies the data within the predetermined time, control the watch-dog timer to determine that the at least one processor is in the normal operation state.

4. The electronic device of claim 1 , wherein the at least one processor is further configured to:

control the watch-dog timer to detect whether the at least one processor is in a lock-up state; and

when the at least one processor is in the lock-up state, control the watch-dog timer to determine that the at least one processor is in the abnormal operation state.

5. The electronic device of claim 1 , wherein the at least one processor is further configured to:

control the watch-dog timer to monitor whether the at least one processor terminates a processing within the predetermined time; and

when the at least one processor does not terminate the processing within the predetermined time, control the watch-dog timer to determine that the at least one processor is in the abnormal operation state.

6. The electronic device of claim 1 , wherein the at least one processor is further configured to:

control the battery to store the power or supply the power to the touch screen and the communication circuitry.

7. The electronic device of claim 1 , wherein the at least one processor is further configured to:

control the power input unit to supply the power to the battery, the touch screen and the communication circuitry from an external power supply device.

8. The electronic device of claim 1 , further comprising:

a first switch connected between the power input unit and a system;

a second switch connected between the battery and a point where the first switch and the system are connected; and

wherein the at least one processor is further configured to control operation of the first switch and the second switch, and

wherein the system includes at least one of the touch screen, the communication circuitry, the memory and the at least one processor.

9. The electronic device of claim 8 , wherein the at least one processor is configured to:

in response to determining that the at least one processor is in the abnormal operation state, control the first switch to block power supplied to the system and the battery through the power input unit, and control the second switch to supply the power to the system through the battery.

10. A method comprising:

controlling a power input unit to supply power to a battery, a touch screen and a communication circuitry in a normal operation state;

controlling the battery to supply the power to the touch screen and the communication circuitry in an abnormal operation state;

controlling a watch-dog timer to monitor whether at least one processor identifies data within a predetermined time;

determining, via the watch-dog timer, when the at least one processor does not identify the data within the predetermined time, that the at least one processor is in the abnormal operation state; and

in response to determining that the at least one processor is in the abnormal operation state, controlling the power input unit to block power supplied to the battery, the touch screen, and the communication circuitry.

11. The method of claim 10 , wherein the data comprises a register bit.

12. The method of claim 10 , further comprising:

determining, via the watch-dog timer, when the at least one processor identifies the data within the predetermined time, that the at least one processor is in the normal operation state.

13. The method of claim 10 , further comprising:

controlling the watch-dog timer to detect whether the at least one processor is in a lock-up state; and

determining, via the watch-dog timer, when the at least one processor is in the lock-up state, that the at least one processor is in the abnormal operation state.

14. The method of claim 10 , further comprising:

controlling the watch-dog timer to monitor whether the at least one processor terminates a processing within the predetermined time; and

determining, via the watch-dog timer, when the at least one processor does not terminate the processing within the predetermined time, that the at least one processor is in the abnormal operation state.

15. The method of claim 10 , further comprising:

controlling the battery to store the power or supply the power to the touch screen and the communication circuitry.

16. The method of claim 10 , further comprising:

controlling the power input unit to supply the power to the battery, the touch screen and the communication circuitry from an external power supply device.

17. The method of claim 10 , further comprising:

in response to determining that the at least one processor is in the abnormal operation state, controlling a first switch to block power supplied to a system and the battery through the power input unit, and controlling to a second switch to supply the power to the system through the battery,

wherein the system includes at least one of the touch screen, the communication circuitry, a memory, and the at least one processor,

wherein the first switch is connected between the power input unit and the system;

wherein the second switch is connected between the battery and a point where the first switch and the system are connected; and

wherein the at least one processor is further configured to control operation of the first switch and the second switch.

Priority Claims (1)
KR 10-2014-0089593 · Jul 16, 2014 · national
Continuity (2)
Continuation 14799698 · Jul 15, 2015
Related Publication 20190146574A1 · May 16, 2019