Programmable interface to in-memory cache processor
The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.
1. A processor, comprising:
memory circuitry that includes a plurality of static random access memory (SRAM) arrays;
processor circuitry to:
compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first programming language to an intermediate domain-specific language (DSL); and
compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), wherein each of the multiple instruction sets corresponds to a respective layer of the multi-layer neural network model; and
memory controller circuitry to:
configure multiple of the SRAM arrays within the plurality of SRAM arrays to operate as serially coupled, pipelined SRAM architecture (PISA) circuitry; and
assign each of the multiple instruction sets to a respective one of the multiple SRAM arrays for execution by the respective one SRAM array.
2. The processor of claim 1 , wherein the first programming language is a high-level programming language of a group that includes one or more of Python, C, C++, R, Lisp, Prolog, or Java.
3. The processor of claim 1 , wherein the intermediate DSL includes a data-flow graph of layer descriptors.
4. The processor of claim 1 wherein each of the multiple SRAM arrays comprises a SRAM array having in-memory integer compute capability (C-SRAM).
5. The processor of claim 1 wherein the system comprises a multi-chip module that includes processor circuitry, the memory circuitry, and the neural network control circuitry.
6. The processor of claim 1 , wherein to compile the representative data from the first programming language to the intermediate DSL includes to generate a data-flow graph of layer descriptors representing the multi-layer neural network model.
7. The processor of claim 6 , wherein to compile the representative data from the intermediate DSL to the multiple instruction sets includes to optimize each layer descriptor within the generated data-flow graph.
8. A non-transitory machine-readable storage device having instructions that, when executed by processing circuitry, cause the processing circuitry to perform neural network processing operations comprising to:
receive, in a first programming language, data representative of a multi-layer neural network model and one or more neural network data inputs;
compile, via the processor circuitry, the data representative of the multi-layer neural network model and the one or more neural network data inputs from the first programming language to an intermediate domain-specific language (DSL);
compile, via the processor circuitry, the data representative of the multi-layer neural network model and the one or more neural network data inputs from the intermediate DSL to multiple instruction sets, each of the multiple instruction sets being in accordance with an instruction set architecture (ISA) and corresponding to a respective layer of the multi-layer neural network model;
configure, via the processor circuitry and memory circuitry that is coupled to the processor circuitry, multiple static random access memory (SRAM) arrays of a plurality of SRAM arrays within the memory circuitry to operate as serially coupled pipelined SRAM architecture (PISA) circuitry; and
assign, via the processor circuitry, each of the multiple instruction sets to a respective one of the multiple SRAM arrays.
9. The non-transitory machine-readable storage device of claim 8 , wherein to compile the representative data from the intermediate DSL to the multiple instruction sets includes using a software stack specific to an in-memory compute accelerator.
10. The non-transitory machine-readable storage device of claim 8 further comprising initiating execution of each of the multiple instruction sets by the respective one of the multiple SRAM arrays.
11. The non-transitory machine-readable storage device of claim 8 wherein each of the multiple SRAM arrays comprises an SRAM array having in-memory integer compute capability (C-SRAM).
12. The non-transitory machine-readable storage device of claim 8 wherein the method is performed via a multi-chip module that includes the processor circuitry and the memory circuitry.
13. The non-transitory machine-readable storage device of claim 8 wherein to compile the representative data from the first programming language to the intermediate DSL includes to generate a data-flow graph of layer descriptors.
14. The non-transitory machine-readable storage device of claim 13 wherein to compile the representative data from the intermediate DSL to the multiple instruction sets includes to optimize each layer descriptor within the generated data-flow graph.
15. A system, comprising:
system memory to store data representative of a multi-layer neural network model and one or more neural network data inputs;
processor circuitry coupled to the system memory, the processor circuitry comprising processor memory circuitry that includes a plurality of static random access memory (SRAM) arrays;
wherein the processor circuitry is to:
compile the data representative of the multi-layer neural network model and the one or more neural network data inputs from a first programming language to an intermediate domain-specific language (DSL);
compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), wherein each of the multiple instruction sets corresponds to a respective layer of the multi-layer neural network model;
configure multiple of the SRAM arrays within the plurality of SRAM arrays to operate as serially coupled, pipelined SRAM architecture (PISA) circuitry; and
assign each of the multiple instruction sets to a respective one of the multiple SRAM arrays for execution by the respective one SRAM array; and
PISA memory circuitry coupled to the system memory and coupled to the processor via the processor memory circuitry.
16. The system of claim 15 , wherein the first programming language is a high-level programming language of a group that includes one or more of Python, C, C++, R, Lisp, Prolog, or Java.
17. The system of claim 15 , wherein the intermediate DSL includes a data-flow graph of layer descriptors.
18. The system of claim 15 wherein each of the multiple SRAM arrays comprises a SRAM array having in-memory integer compute capability (C-SRAM).
19. The system of claim 15 wherein the system comprises a multi-chip module that includes the processor circuitry and the processor memory circuitry.
20. The system of claim 15 , wherein to compile the representative data from the first programming language to the intermediate DSL includes to generate a data-flow graph of layer descriptors representing the multi-layer neural network model.
21. The system of claim 20 , wherein to compile the representative data from the intermediate DSL to the multiple instruction sets includes to optimize each layer descriptor within the generated data-flow graph.