Flip chip package utilizing trace bump trace interconnection
A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.
1. A flip chip package, comprising:
a substrate having a die attach surface; and
a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface, wherein at least one of the plurality of conductive pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate, and wherein the at least one of the plurality of conductive pillar bumps is directly jointed to the trace, wherein the conductive pillar bump has a lower stress side that is closer to a center of the die and a higher stress side that is father away from the center of the die along a lengthwise direction, wherein the conductive pillar bump comprises an asymmetric plug configuration along the lengthwise direction, and wherein the asymmetric plug configuration comprises an integral plug disposed on the lower stress side of the conductive pillar bump along the lengthwise direction.
2. The flip chip package according to claim 1 wherein at least one of the plurality of conductive pillar bumps has a bump length that is at least two times greater than the line width of the trace.
3. The flip chip package according to claim 1 wherein at least one of the plurality of conductive pillar bumps is oval-shaped from a plan view.
4. The flip chip package according to claim 1 wherein the line width of the trace is between 10 μm and 40 μm.
5. The flip chip package according to claim 1 wherein the die has a bump pitch between 120 μm and 180 μm.
6. The flip chip package according to claim 1 wherein at least one of the plurality of conductive pillar bumps has a bump width between 10 μm and 40 μm and a bump length between 40 μm and 80 μm.
7. The flip chip package according to claim 1 wherein at least one of the plurality of conductive pillar bumps has a bump orientation that is directed to the center of the die.
8. The flip chip package according to claim 1 further comprising an underfill between the die and the substrate.
9. The flip chip package according to claim 8 wherein the underfill comprises capillary underfill (CUF), molded underfill (MUF) or a combination thereof.
10. The flip chip package according to claim 1 wherein at least one of the plurality of conductive pillar bumps is composed of a metal stack comprising an UBM layer, a conductive layer, and a solder cap.
11. The flip chip package according to claim 10 wherein the conductive layer has a thickness between 30 μm and 60 μm.
12. The flip chip package according to claim 10 wherein the solder cap has a thickness between 10 μm and 40 μm.
13. The flip chip package according to claim 10 wherein at least one of the plurality of conductive pillar bumps further comprises a nickel layer between the conductive layer and the solder cap.
14. A flip chip package, comprising:
a substrate having a die attach surface; and
a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface, wherein at least one of the plurality of conductive pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate, and wherein no substrate via is interposed between the at least one of the plurality of conductive pillar bumps and the trace, wherein the conductive pillar bump has a lower stress side that is closer to a center of the die and a higher stress side that is father away from the center of the die along a lengthwise direction, wherein the conductive pillar bump comprises an asymmetric plug configuration along the lengthwise direction, and wherein the asymmetric plug configuration comprises an integral plug disposed on the lower stress side of the conductive pillar bump along the lengthwise direction.
15. The flip chip package according to claim 14 wherein at least one of the plurality of conductive pillar bumps has a bump length that is at least two times greater than the line width of the trace.
16. The flip chip package according to claim 14 wherein at least one of the plurality of conductive pillar bumps is oval-shaped from a plan view.
17. The flip chip package according to claim 14 wherein at least one of the plurality of conductive pillar bumps has a bump orientation that is directed to the center of the die.
18. The flip chip package according to claim 14 further comprising an underfill between the die and the substrate.
19. The flip chip package according to claim 14 wherein at least one of the plurality of conductive pillar bumps is composed of a metal stack comprising an UBM layer, a conductive layer, and a solder cap.
20. The flip chip package according to claim 19 wherein at least one of the plurality of conductive pillar bumps further comprises a nickel layer between the conductive layer and the solder cap.