Vertical fin field effect transistor device with reduced gate variation and reduced capacitance
A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.
1. A method of forming a fin field effect transistor device, comprising:
forming a vertical fin on a semiconductor substrate, wherein the vertical fin is the same material as the semiconductor substrate;
depositing a sidewall liner on exposed surfaces of the vertical fin;
removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin;
laterally etching the support pillar to form a thinned support pillar; and
forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.
2. The method of claim 1 , further comprising depositing a capping layer on the bottom source/drain layer.
3. The method of claim 2 , further comprising converting the capping layer to a bottom spacer layer.
4. The method of claim 3 , wherein the capping layer is converted to the bottom spacer layer through exposure to an oxidizing agent at a temperature in a range of about 400° C. to about 800° C.
5. The method of claim 3 , wherein the capping layer is silicon-germanium.
6. The method of claim 5 , wherein the capping layer has a germanium concentration in a range of about 40 atomic percent (at. %) to about 60 at. %.
7. The method of claim 3 , further comprising removing the sidewall liner, and forming a gate dielectric layer on the vertical fin, bottom spacer layer, and bottom source/drain layer.
8. The method of claim 7 , wherein the gate dielectric layer has a thickness less than or equal to the distance between a proximal edge of the bottom spacer layer and the thinned support pillar.
9. The method of claim 7 , further comprising forming a conductive gate fill on the gate dielectric layer, and forming a top spacer layer on the conductive gate fill.
10. A method of forming a fin field effect transistor device, comprising:
forming a vertical fin on a substrate;
depositing a sidewall liner on exposed surfaces of the vertical fin;
removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin;
laterally etching the support pillar to form a thinned support pillar;
forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a recessed dimple; and
depositing a capping layer in the recessed dimple.
11. The method of claim 10 , wherein the capping layer has a lune shape.
12. The method of claim 10 , wherein the thinned support pillar has a width in a range of about 3 nm to about 6 nm.
13. The method of claim 10 , further comprising converting the capping layer to a bottom spacer layer, wherein the bottom spacer layer has a lens shape.
14. The method of claim 10 , wherein the capping layer is silicon-germanium with a germanium concentration in a range of about 40 atomic percent (at. %) to about 60 at. %.
15. The method of claim 14 , wherein the capping layer is converted to the bottom spacer layer through exposure to an oxidizing agent at a temperature in a range of about 400° C. to about 800° C.