Transport block size determination in mobile communications
Various solutions for transport block size (TBS) determination with respect to user equipment and network apparatus in mobile communications are described. An apparatus may determine an intermediate number of information bits. The apparatus may quantize the intermediate number of information bits. The apparatus may determine a TBS according to the quantized intermediate number of information bits. The apparatus may transmit the information bits according to the TBS.
1. A method, comprising:
determining, by a processor of an apparatus, an intermediate number of information bits;
quantizing, by the processor, the intermediate number of information bits;
determining, by the processor, a transport block size (TBS) according to the quantized intermediate number of information bits;
transmitting, by the processor, the information bits according to the TBS; and
determining, by the processor, a step size by a power of 2,
wherein the intermediate number is proportional to a modulation order and a coding rate,
wherein the information bits comprise data bits, control bits, or a combination thereof,
wherein the quantizing comprises quantizing the intermediate number of information bits by the step size,
wherein the step size is configurable and comprises a minimum value, and
wherein an exponent of 2 is determined according to a logarithm function of the intermediate number of information bits.
2. The method of claim 1 , further comprising:
determining, by the processor, the exponent according to at least one a cyclic redundancy check (CRC) length and a configurable offset constant.
3. The method of claim 1 , further comprising:
determining, by the processor, the TBS according to at least one of a number of code blocks, a code block size, and a cyclic redundancy check (CRC) length.
4. The method of claim 1 , further comprising:
determining, by the processor, the code block size based on the step size being one byte.
5. The method of claim 1 , further comprising:
determining, by the processor, the intermediate number of information bits according to at least one of a number of resource element, a coding rate, a scheduled modulation order, and a signaled number of layers.
6. The method of claim 1 , further comprising:
comparing, by the processor, the intermediate number of information bits with a threshold value; and
determining, by the processor, the TBS according to a comparison result.
7. The method of claim 1 , further comprising:
determining, by the processor, whether the intermediate number of information bits is greater than a threshold value; and
determining, by the processor, a first step size for quantizing the intermediate number of information bits when the intermediate number of information bits is not greater than the threshold value.
8. The method of claim 1 , further comprising:
determining, by the processor, whether the intermediate number of information bits is greater than a threshold value; and
determining, by the processor, a second step size for quantizing the intermediate number of information bits when the intermediate number of information bits is greater than the threshold value.
9. An apparatus, comprising:
a transceiver capable of wirelessly communicating with a plurality of nodes of a wireless network; and
a processor communicatively coupled to the transceiver, the processor capable of:
determining an intermediate number of information bits;
quantizing the intermediate number of information bits;
determining a transport block size (TBS) according to the quantized intermediate number of information bits;
transmitting, via the transceiver, the information bits according to the TBS;
determining a step size by a power of 2,
wherein the intermediate number is proportional to a modulation order and a coding rate,
wherein the information bits comprise data bits, control bits, or a combination thereof,
wherein the quantizing comprises quantizing the intermediate number of information bits by the step size,
wherein the step size is configurable and comprises a minimum value, and
wherein an exponent of 2 is determined according to a logarithm function of the intermediate number of information bits.
10. The apparatus of claim 9 , wherein the processor is further capable of:
determining the exponent according to at least one a cyclic redundancy check (CRC) length and a configurable offset constant.
11. The apparatus of claim 9 , wherein the processor is further capable of:
determining the TBS according to at least one of a number of code blocks, a code block size, and a cyclic redundancy check (CRC) length.
12. The apparatus of claim 9 , wherein the processor is further capable of:
determining the code block size based on the step size being one byte.
13. The apparatus of claim 9 , wherein the processor is further capable of:
determining the intermediate number of information bits according to at least one of a number of resource element, a coding rate, a scheduled modulation order, and a signaled number of layers.
14. The apparatus of claim 9 , wherein the processor is further capable of:
comparing the intermediate number of information bits with a threshold value; and
determining the TBS according to a comparison result.
15. The apparatus of claim 9 , wherein the processor is further capable of:
determining whether the intermediate number of information bits is greater than a threshold value; and
determining a first step size for quantizing the intermediate number of information bits when the intermediate number of information bits is not greater than the threshold value.
16. The apparatus of claim 9 , wherein the processor is further capable of:
determining whether the intermediate number of information bits is greater than a threshold value; and
determining a second step size for quantizing the intermediate number of information bits when the intermediate number of information bits is greater than the threshold value.