Clock generator and clock generation method
View Patent ↗According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.
1. A clock generator comprising:
a frequency divider which generates a divided frequency clock of a frequency lower than a frequency of a source clock by performing mask processing on part of a pulse train of the source clock;
wherein the frequency divider selectively generates the divided frequency clock by selectively using one of a plurality of different bit string patterns stored in a memory to mask the pulse train of the source clock at fixed periods, wherein the plurality of bit strings mask different numbers of pulses of the pulse train.
2. The clock generator according to claim 1 , wherein the frequency divider switches the frequency of the divided frequency clock to be generated by switching the bit string pattern to be used.
3. The clock generator according to claim 2 , wherein the frequency divider switches the bit string pattern to be used under control of predetermined hardware.
4. The clock generator according to claim 1 , further comprising a controller that changes the frequency of the divided frequency clock generated by the frequency divider in accordance with a status change of a certain object.
5. The clock generator according to claim 4 , wherein the controller changes the frequency of the divided frequency clock generated by the frequency divider in accordance with an occurrence of one or a plurality of transactions.
6. The clock generator according to claim 4 , wherein the controller changes the frequency of the divided frequency clock generated by the frequency divider in accordance with an available capacity of a memory that sends data to a predetermined device.
7. The clock generator according to claim 4 , wherein the controller changes the frequency of the divided frequency clock generated by the frequency divider in accordance with a temperature in a predetermined location.
8. The clock generator according to claim 4 , wherein the controller changes the frequency of the divided frequency clock generated by the frequency divider in accordance with a transition of an operation mode.
9. A clock generation method comprising:
preparing a plurality of different bit string patterns which mask different numbers of pulses of a pulse train of a source clock at fixed periods, and storing the plurality of different bit string patterns in a memory;
inputting the source clock into a frequency divider;
selecting one of the plurality of bit string patterns from the memory; and
generating a divided frequency clock of a frequency lower than a frequency of the source clock by the frequency divider by performing mask processing on part of the pulse train of the source clock using the selected bit string pattern.
10. The clock generation method according to claim 9 , further comprising:
switching the frequency of the divided frequency clock to be generated by the frequency divider by switching the bit string pattern to be used.