Non-volatile memory device including memory planes, and operating method thereof
A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.
1. A non-volatile memory device, comprising:
a memory chip, including
a first semiconductor layer including a memory cell array, the memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals, and
a second semiconductor layer including a control circuit configured to
monitor operations of the plurality of memory planes to obtain a monitoring result, and
control an operation of at least one of the plurality of memory planes based on the monitoring result such that a plurality of peak power intervals of the plurality of memory planes are at least partially distributed,
wherein the first semiconductor layer is above the second semiconductor layer, and the memory chip has a cell over periphery (COP).
2. The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:
delay the operation of the at least one of the plurality of memory planes when the plurality of peak power intervals of at least some of the plurality of memory planes overlap each other.
3. The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:
monitor whether an operation of each of the plurality of memory planes enters a corresponding peak power interval among the plurality of peak power intervals, and
generate a monitoring signal based on a result of the monitoring.
4. The non-volatile memory device of claim 1 , wherein the plurality of peak power intervals correspond to at least one of a bit line setup interval for a program operation, a bit line precharge interval for a read operation, or a latch initialization interval before a program operation or a read operation.
5. The non-volatile memory device of claim 1 , wherein
the control circuit includes a plurality of control logics, each of the plurality of control logics corresponding to a respective memory plane of the plurality of memory planes, and
each of the plurality of control logics is configured to
monitor whether an operation of the respective memory plane enters a peak power interval among the plurality of peak power intervals to obtain a respective monitoring result,
generate a respective monitoring signal based on the respective monitoring result, and
provide the respective monitoring signal to other control logics of the plurality of control logics.
6. The non-volatile memory device of claim 5 , wherein each of the plurality of control logics is further configured to:
determine a priority of each the plurality of memory planes using priority information; and
control the operation of the at least one of the plurality of memory planes based on a monitoring signal associated with another memory plane among the plurality of memory planes having a higher priority than the at least one of the plurality of memory planes.
7. The non-volatile memory device of claim 6 , wherein information about the plurality of peak power intervals or the priority information is obtained based on a set feature command received from a memory controller.
8. The non-volatile memory device of claim 5 , wherein
the plurality of memory planes includes a first memory plane and a second memory plane,
the plurality of control logics includes
a first control logic configured to
generate a first monitoring signal corresponding to the first memory plane, and
control an operation of the first memory plane based on a second monitoring signal when the operation of the first memory plane enters a peak power interval among the plurality of peak power intervals, and
a second control logic configured to generate the second monitoring signal corresponding to the second memory plane.
9. The non-volatile memory device of claim 8 , wherein the first control logic is further configured to:
delay the operation of the first memory plane when an operation of the second memory plane is in a corresponding peak power interval among the plurality of peak power intervals, and
allow the operation of the first memory plane to be performed when the operation of the second memory plane is outside the corresponding peak power interval.
10. The non-volatile memory device of claim 9 , wherein the first control logic is further configured to:
delay the operation of the first memory plane until the second monitoring signal is changed.
11. The non-volatile memory device of claim 9 , wherein the first control logic is further configured to:
delay the operation of the first memory plane for a certain time.
12. A non-volatile memory device, comprising:
a memory chip, including
a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals, and
a control circuit configured to control an operation of at least one of the plurality of memory planes such that a plurality of peak power intervals of the plurality of memory planes are at least partially distributed, the control circuit including a plurality of control logics, each of the plurality of control logics corresponding to a respective memory plane of the plurality of memory planes,
the plurality of memory planes includes a first memory plane and a second memory plane,
the plurality of control logics includes:
a first control logic configured to
generate a first monitoring signal corresponding to the first memory plane, and
control an operation of the first memory plane based on a second monitoring signal when the operation of the first memory plane enters a peak power interval among the plurality of peak power intervals, and
a second control logic configured to generate the second monitoring signal corresponding to the second memory plane.
13. The non-volatile memory device of claim 12 , wherein
the control circuit is further configured to delay an operation of the at least one of the plurality of memory planes to distribute the plurality of peak power intervals when the plurality of peak power intervals of the plurality of memory planes overlap each other,
the memory cell array is above the control circuit, and
the memory chip has a cell over periphery (COP) structure.
14. The non-volatile memory device of claim 12 , wherein the at least one of the plurality of memory planes is determined based on priority information of each of the plurality of memory planes.
15. An operating method performed by a control circuit of a non-volatile memory device including a memory chip, the operating method comprising:
monitoring operations of a plurality of memory planes included in the memory chip;
determining whether an operation of at least one of the plurality of memory planes corresponds to a peak power interval;
determining whether an operation of another memory plane of the plurality of memory planes corresponds to the peak power interval when the operation of the at least one of the plurality of memory planes corresponds to the peak power interval; and
controlling the operations of the plurality of memory planes such that a plurality of peak power intervals including the peak power interval are at least partially distributed when the operation of the other memory plane corresponds to the peak power interval, the controlling being based on priority information of each of the plurality of memory planes.
16. The operating method of claim 15 , further comprising:
determining the other memory plane using the priority information before the determining of whether the operation of the other memory plane corresponds to the peak power interval.
17. The operating method of claim 16 , further comprising:
receiving the priority information or information about the peak power interval from a memory controller before the monitoring.
18. The operating method of claim 15 , wherein the controlling includes performing the operation of the at least one of the plurality of memory planes when the operation of the at least one of the plurality of memory planes does not correspond to the peak power interval or the operation of the other memory plane does not correspond to the peak power interval.
19. The operating method of claim 15 , wherein the controlling includes suspending the operation of the at least one of the plurality of memory planes until the operation of the other memory plane deviates from the peak power interval.
20. The operating method of claim 15 , wherein the controlling includes suspending the operation of the at least one of the plurality of memory planes during a certain time.