IP Library Granted Patent US 10,713,549
Granted Patent B1
US 10,713,549 · App. 15/985,291 · Granted Jul 14, 2020

RFID tag rectifiers with bias current reuse

Inventors: Charles J. T. Peach (Seattle, WA); John D. Hyde (Corvallis, OR); Jay A. Kuhn (Seattle, WA); Theron Stanford (Seattle, WA); Amita Patil (Seattle, WA)
Assignee: Impinj, Inc.
G06K19/0715H03K17/6872G06K19/0701G06K19/0707G06K19/0709G06K19/0713G06K19/0723
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Quick Facts
Patent No.
US 10,713,549
App. No.
15/985,291
Granted
Jul 14, 2020
Kind
B1
Abstract

Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. Thee bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.

Claims (20)

1. A rectifier for a Radio Frequency Identification (RFID) integrated circuit (IC), the rectifier comprising:

at least first and second rectifier stages, each rectifier stage having at least one rectifying element, the rectifying elements in the rectifier stages forming a main current path of the rectifier; and

a first bias current path different from the main current path and passing through a ladder of sequentially arranged resistive elements, the first bias current path configured to:

pass a first bias current through the ladder;

use the first bias current to bias a rectifying element in the first rectifier stage; and

reuse the first bias current to generate, using one or more of the resistive elements, a voltage-bias for a rectifying element in the second rectifier stage.

2. The rectifier of claim 1 , further comprising a second bias current path passing a second bias current, wherein:

the at least one rectifying element in each of the rectifier stages includes an NMOS transistor and a PMOS transistor;

the first bias current path is configured to reuse the first bias current to generate a voltage-bias for an NMOS transistor in the second rectifier stage; and

the second bias current path is configured to:

use the second bias current to bias a PMOS transistor in the first rectifier stage; and

reuse the second bias current to generate a voltage-bias for a PMOS transistor in the second rectifier stage.

3. The rectifier of claim 1 , wherein:

a voltage between two adjacent resistive elements of the ladder track a corresponding voltage on the main current path.

4. The rectifier of claim 1 , wherein the resistive elements include source-follower-configured transistors.

5. The rectifier of claim 1 , wherein the first bias current path at least one of originates and ends in the main current path.

6. The rectifier of claim 1 , wherein a number of rectifier stages in the rectifier exceeds a number of bias current paths in the rectifier.

7. The rectifier of claim 1 , further comprising a bias adjust controller configured to adjust a reference current used to generate the first bias current.

8. The rectifier of claim 1 , wherein the resistive elements include resistors.

9. The rectifier of claim 1 , wherein the resistive elements include variable resistors.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2018
From: PATIL, AMITA
To: IMPINJ, INC.
Reel/Frame 045875/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2018
From: PEACH, CHARLES J.T.; HYDE, JOHN D.; KUHN, JAY A.; STANFORD, THERON
To: IMPINJ, INC.
Reel/Frame 045864/0565 →
Continuity (1)
Provisional Application 62509777 · May 23, 2017
Cited By (5)
US 12,204,970 US 12,223,814 US 12,524,640 US 12,536,401 US 12,537,460