RFID tag rectifiers with bias current reuse
Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. Thee bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.
1. A rectifier for a Radio Frequency Identification (RFID) integrated circuit (IC), the rectifier comprising:
a plurality of rectifier stages, each rectifier stage having at least one rectifying element, the rectifying elements in the rectifier stages forming a main current path of the rectifier; and
a bias current path different from the main current path and configured to direct a single bias current to simultaneously bias a respective rectifying element of each of the rectifier stages of the plurality of rectifier stages by using the single bias current to at least partly current-bias a first rectifying element in a first rectifier stage of the plurality of rectifier stages and reusing the single bias current to voltage-bias at least a second rectifying element in at least a second rectifier stage of the plurality of rectifier stages.
2. The rectifier of claim 1 , further comprising another bias current path, wherein:
the at least one rectifying element in each of the rectifier stages includes an NMOS transistor and a PMOS transistor;
the bias current path is configured to direct a first bias current to simultaneously bias a respective NMOS transistor of each of the rectifier stages; and
the other bias current path is configured to direct a second bias current to simultaneously bias a respective PMOS transistor of each of the rectifier stages.
3. The rectifier of claim 1 , wherein:
a biasing transistor is configured to current-bias the first rectifying element; and
a gate of the second rectifying element is voltage-biased.
4. The rectifier of claim 1 , wherein:
the bias current path includes a ladder of resistive elements arranged sequentially, and
a voltage between two adjacent resistive elements of the ladder tracks a corresponding voltage on the main current path.
5. The rectifier of claim 4 , wherein the resistive elements include source-follower-configured transistors.
6. The rectifier of claim 1 , wherein the bias current path originates from and/or terminates at one or more current mirrors.
7. The rectifier of claim 1 , wherein the bias current path originates from and/or terminates at the main current path.
8. The rectifier of claim 1 , wherein the bias current path originates from and/or terminates at another rectifier.
9. A method to bias a rectifier having a plurality of rectifier stages coupled together serially, the method comprising:
providing, through a main current path of the rectifier, a main current to at least one rectifying element of each rectifier stage of the plurality of rectifier stages, wherein rectifying elements in the plurality of rectifier stages form the main current path of the rectifier; and
providing, through a bias current path different from the main current path, a first bias current to simultaneously bias a respective rectifying element of each of the plurality of rectifier stages by using the first bias current to at least partly current-bias a first rectifying element in a first rectifier stage of the plurality of rectifier stages and reusing the first bias current to voltage-bias at least a second rectifying element in at least a second rectifier stage of the plurality of rectifier stages.
10. The method of claim 9 , further comprising:
providing, through another bias current path different from the bias current path, a second bias current, wherein
the at least one rectifying element in each of the plurality of rectifier stages includes an NMOS transistor and a PMOS transistor;
the first bias current is configured to simultaneously bias a respective NMOS transistor of each of the plurality of rectifier stages; and
the second bias current is configured to simultaneously bias a respective PMOS transistor of each of the plurality of rectifier stages.
11. The method of claim 9 , further comprising:
using a biasing transistor configured to current-bias the first rectifying element; and
voltage-biasing a gate of the at least second rectifying element.
12. The method of claim 9 , wherein the bias current path includes a ladder of resistive elements arranged sequentially, and the method further comprises:
causing a voltage between two adjacent resistive elements of the ladder to track a corresponding voltage on the main current path.
13. The method of claim 12 , wherein the resistive elements include source-follower-configured transistors.
14. The method of claim 9 , wherein the bias current path originates from and/or terminates at:
one or more current mirrors,
the main current path, or
another rectifier.
15. A rectifier comprising:
at least three rectifier stages, each of the rectifier stages having at least one rectifying element, the rectifying elements in the at least three rectifier stages forming at least part of a main current path of the rectifier; and
a bias current path different from the main current path and configured to direct a single bias current to simultaneously bias a respective rectifying element of each of the at least three rectifier stages by using the single bias current to at least partly current-bias a first rectifying element in a first rectifier stage of the plurality of rectifier stages and reusing the single bias current to voltage-bias at least a second rectifying element in at least a second rectifier stage of the plurality of rectifier stages.
16. The rectifier of claim 15 , further comprising another bias current path, wherein:
the at least one rectifying element in each of the rectifier stages includes an NMOS transistor and a PMOS transistor;
the bias current path is configured to direct a first bias current to simultaneously bias a respective NMOS transistor of each of the rectifier stages; and
the other bias current path is configured to direct a second bias current to simultaneously bias a respective PMOS transistor of each of the rectifier stages.
17. The rectifier of claim 15 , wherein:
a biasing transistor is configured to current-bias the first rectifying element; and
a gate of the second rectifying element is voltage-biased.
18. The rectifier of claim 15 , wherein:
the bias current path includes a ladder of resistive elements arranged sequentially, and
a voltage between two adjacent resistive elements of the ladder track a corresponding voltage on the main current path.
19. The rectifier of claim 18 , wherein the resistive elements include source-follower-configured transistors.
20. The rectifier of claim 15 , wherein the single bias current is generated by:
at least one current mirror,
the rectifier, or
another rectifier.