Semiconductor structure and method for manufacturing the same
A method of manufacturing a semiconductor structure includes the following operations. A wafer with an orientation mark at a first crystal orientation represented by a family of Miller indices comprising <ijk> is provided, wherein i 2+ j 2+ k 2 =2. A first chip and a second chip are connected to a first surface of the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. The direction is not parallel to the first crystal orientation.
1. A semiconductor structure, comprising:
a wafer comprising a crystal orientation represented by a family of Miller indices comprising <ijk>, wherein i 2 +j 2 +k 2 =2;
a circuit layer; and
a first chip mounted on the wafer through the circuit layer, wherein a first edge of the first chip is arranged in a direction, the direction is not parallel to the crystal orientation, and the first chip includes a plurality of conductive pads facing and electrically connected to the circuit layer.
2. The semiconductor structure of claim 1 , wherein an included angle between the direction and the crystal orientation is greater than 0 degree and less than 90 degrees.
3. The semiconductor structure of claim 2 , wherein the included angle between the direction and the crystal orientation is between about 30 degrees and about 60 degrees.
4. The semiconductor structure of claim 3 , wherein the included angle between the direction and the crystal orientation is about 45 degrees.
5. The semiconductor structure of claim 1 , further comprising a second chip over the wafer, wherein a second edge of the second chip is adjacent to the first edge, forming a boundary extending in the direction between the first edge and the second edge.
6. The semiconductor structure of claim 1 , wherein the wafer comprises
a body;
wherein the circuit layer is formed over a first surface of the body, and electrically connected to the first chip.
7. The semiconductor structure of claim 6 , further comprising a substrate connected to a second surface of the body.
8. The semiconductor structure of claim 7 , further comprising:
a plurality of conductive structures between the second surface and the substrate; and
an underfill layer between the second surface and the substrate.
9. A semiconductor structure, comprising:
a wafer comprising a crystal orientation represented by a family of Miller indices comprising <ijk>, wherein i 2 +j 2 +k 2 =2;
a plurality of conductive pads and a plurality of conductive bumps;
a first chip and a second chip mounted on the wafer through the plurality of conductive pads and the plurality of conductive bumps, wherein a first edge of the first chip and a second edge of the second chip are adjacent to each other, forming a boundary extending in a direction between the first edge and the second edge, and an included angle between the direction and the crystal orientation is greater than 0 degree and less than 90 degrees; and
a plurality of interconnection structures in a body of the wafer.
10. The semiconductor structure of claim 9 , wherein a pattern of the interconnection structures is corresponding to a bonding position of the first chip and the second chip.
11. The semiconductor structure of claim 9 , wherein the first chip and the second chip are electrically connected to the interconnection structures through the plurality of conductive pads and the plurality of conductive bumps.
12. The semiconductor structure of claim 9 , wherein the interconnection structures comprise through substrate vias extending from a first surface of the body of the wafer to a second surface of the body of the wafer.
13. The semiconductor structure of claim 12 , further comprising a redistribution layer formed on the first surface of the body of the wafer for coupling with the through substrate vias.
14. The semiconductor structure of claim 13 , wherein the plurality of conductive pads are formed on the redistribution layer.
15. The semiconductor structure of claim 9 , wherein the wafer stacked with the first chip and the second chip is mounted on a substrate.
16. A semiconductor structure, comprising:
a wafer comprising a crystal orientation represented by a family of Miller indices comprising <ijk>, wherein i 2 +j 2 +k 2 =2;
a circuit layer; and
a first chip, a second chip and a third chip electrically connected to the wafer through the circuit layer, wherein the second chip and the third chip are disposed adjacent to different sides of the first chip, a first boundary is formed between the second chip and the first chip extending in a first direction, and a second boundary is formed between the third chip and the first chip extending in a second direction, a first included angle between the first direction and the crystal orientation is greater than 0 degree and less than 90 degrees, a second included angle between the second direction and the crystal orientation is greater than 0 degree and less than 90 degrees, and the circuit layer is between the first chip and the wafer, between the second chip and the wafer and between the third chip and the wafer.
17. The semiconductor structure of claim 16 , wherein the second chip and the third chip are disposed adjacent to two opposite sides.
18. The semiconductor structure of claim 16 , wherein the second boundary is parallel to the first boundary.
19. The semiconductor structure of claim 16 , wherein the first included angle and the second included angle are complementary angles.
20. The semiconductor structure of claim 16 , wherein the second direction is perpendicular to the first direction.