Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such

1. An apparatus comprising:

a substrate;

a first active device adjacent to the substrate;

a first set of one or more layers to interconnect with the first active device;

a second set of one or more layers;

a second active or passive device coupled to the second set of one or more layers; and

a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets,

wherein the substrate, the first active device, and the first set of one or more layers are on a first wafer, wherein the second set of one or more layers and the second active device are on a second wafer, wherein the layer to bond extends along an entire surface of one of the first or second wafers, wherein the layer includes metal, and wherein the metal includes Cu, Ni, Co, Al, or W.

2. The apparatus of claim 1 , wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

3. The apparatus of claim 2 , wherein the bulk silicon includes device quality Epi.

4. The apparatus of claim 1 , wherein the second active or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.

5. The apparatus of claim 1 , wherein the second set of one or more layers includes a layer which is to couple to a package solder bump, and wherein the layer of the second set is coupled to the second active and/or passive device.

6. A method comprising:

forming a substrate;

fabricating a first active device adjacent to the substrate;

forming a first set of one or more layers to interconnect with the first active device;

forming a second set of one or more layers;

fabricating a second active or passive device adjacent to the second set of one or more layers;

forming a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets;

dry etching a surface of the second wafer such that pads are exposed; and

forming solder bumps on the exposed pads.

7. The method of claim 6 , wherein the substrate, the first active device, and the first set of one of more layers are on a first wafer, and wherein the second set of one or more layers and the second active and/or passive device are on a second wafer.

8. The method of claim 6 , wherein the second active or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.

9. The method of claim 6 , wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

10. The method of claim 9 , wherein the bulk silicon includes device quality Epi.

11. The method of claim 6 , wherein the layer to bond includes at least one of a dielectric or a metal.

12. The method of claim 11 , wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue, and wherein the metal includes one of: Cu, Ni, Co, Al, or W.

13. A system comprising:

a memory;

a processor coupled to the memory, the processor having an apparatus which comprises:

a substrate;

a first active device adjacent to the substrate;

a first set of one or more layers to interconnect with the first active device;

a second set of one or more layers;

a second active or passive device coupled to the second set of one or more layers; and

a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets;

wherein the substrate, the first active device, and the first set of one or more layers are on a first wafer, wherein the second set of one or more layers and the second active device are on a second wafer, wherein the layer to bond extends along an entire surface of one of the first or second wafers, and wherein the layer includes dielectric, and wherein the dielectric includes carbon-doped oxide; and

a wireless interface to allow the processor to communicate with another device.

14. The system of claim 13 , wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

15. The system of claim 14 , wherein the bulk silicon includes device quality Epi.