IP Library › Granted Patent US 10,714,466
Granted Patent B1
US 10,714,466 · App. 16/255,786 · Granted Jul 14, 2020

Layout pattern for magnetoresistive random access memory

Inventors: Chung-Liang Chu (Kaohsiung, TW); Chih-Hsien Tang (Tainan, TW); Yu-Ruei Chen (New Taipei, TW); Ya-Huei Tsai (Tainan, TW); Rai-Min Huang (Taipei, TW); Chueh-Fei Tai (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L27/0207G03F1/36H01L27/222H01L27/224H01L27/228H01L43/02H01L43/12
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Quick Facts
Patent No.
US 10,714,466
App. No.
16/255,786
Granted
Jul 14, 2020
Kind
B1
Abstract

A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

Claims (23)

1. A layout pattern for magnetoresistive random access memory (MRAM), comprising:

a first magnetic tunneling junction (MTJ) pattern on a substrate;

a second MTJ pattern adjacent to the first MTJ pattern; and

a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement, the first MTJ pattern comprises a circle while the first metal interconnection pattern comprises an ellipse, and the first MTJ pattern and the second MTJ pattern are on a same level.

2. The layout pattern for MRAM of claim 1 , wherein the first metal interconnection pattern is disposed along a first direction relative to the first MTJ pattern and the second MTJ pattern is disposed along a second direction relative to the first metal interconnection.

3. The layout pattern for MRAM of claim 2 , wherein the second MTJ pattern is disposed along a third direction relative to the first MTJ pattern.

4. The layout pattern for MRAM of claim 3 , wherein an angle included by the first direction and the third direction is less than 90 degrees.

5. The layout pattern for MRAM of claim 3 , wherein the first direction, the second direction, and the third direction comprise a triangle.

6. The layout pattern for MRAM of claim 3 , further comprising a second metal interconnection pattern disposed along the first direction relative to the second MTJ pattern.

7. The layout pattern for MRAM of claim 6 , wherein the second metal interconnection pattern is disposed along the third direction relative to the first metal interconnection pattern.

8. The layout pattern for MRAM of claim 6 , further comprising a third metal interconnection pattern disposed along the first direction and around the second MTJ pattern and the second metal interconnection pattern.

9. The layout pattern for MRAM of claim 8 , wherein the third metal interconnection pattern comprises a rectangle.

10. A layout pattern for magnetoresistive random access memory (MRAM), comprising:

a magnetic tunneling junction (MTJ) pattern on a substrate, wherein the MTJ pattern comprises a first L-shape; and

a first metal interconnection pattern adjacent to the MTJ pattern, wherein the first metal interconnection pattern comprises a second L-shape.

11. The layout pattern for MRAM of claim 10 , wherein the MTJ pattern comprises a first portion extending along a first direction and a second portion extending along a second direction and the first metal interconnection pattern comprises a third portion extending along the first direction and a fourth portion extending along the second direction.

12. The layout pattern for MRAM of claim 11 , wherein the first direction is orthogonal to the second direction.

13. The layout pattern for MRAM of claim 11 , wherein the first portion comprises a first via pattern and the third portion comprises a second via pattern.

14. The layout pattern for MRAM of claim 13 , wherein the first via pattern and the second via pattern are disposed diagonally.

15. The layout pattern for MRAM of claim 14 , wherein each of the first via pattern and the second via pattern comprises a circle.

16. The layout pattern for MRAM of claim 10 , further comprising a second metal interconnection pattern adjacent to two sides of the MTJ pattern.

17. The layout pattern for MRAM of claim 16 , wherein the second metal interconnection pattern comprises a rectangle.

18. The layout pattern for MRAM of claim 10 , wherein the MTJ pattern and the first metal interconnection pattern are on a same level.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2019
From: CHU, CHUNG-LIANG; TANG, CHIH-HSIEN; CHEN, YU-RUEI; TSAI, YA-HUEI; HUANG, RAI-MIN; TAI, CHUEH-FEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 048114/0847 →
Priority Claims (1)
CN 2018 1 1610931 · Dec 27, 2018 · national
Cited By (1)
US 12,200,947