IP Library Granted Patent US 12,200,947
Granted Patent B2
US 12,200,947 · App. 18/395,762 · Granted Jan 14, 2025

Magnetoresistive random access memory

Inventors: Ting-Hsiang Huang (Tainan, TW); Yi-Chung Sheng (Tainan, TW); Sheng-Yuan Hsueh (Tainan, TW); Kuo-Hsing Lee (Hsinchu County, TW); Chih-Kai Kang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10B61/10H10N50/10H10N50/80
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Quick Facts
Patent No.
US 12,200,947
App. No.
18/395,762
Granted
Jan 14, 2025
Kind
B2
Abstract

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Claims (13)

1. A semiconductor device, comprising:

a substrate having a magnetic tunneling junction (MTJ) region and a logic region;

a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle;

a first metal interconnection on the MTJ, wherein a top view of the first metal interconnection comprises an ellipse overlapping the circle and the circle contacts the ellipse directly; and

a second metal interconnection on the logic region, wherein the first metal interconnection and the second metal interconnection comprise different shapes.

2. The semiconductor device of claim 1 , wherein the ellipse comprises:

a first curve on one side of the circle; and

a second curve on another side of the circle.

3. The semiconductor device of claim 1 , wherein the ellipse comprises a long axis extending along a first direction and a ratio of the long axis to a diameter of the circle is greater than 2 and less than 3.3.

4. The semiconductor device of claim 3 , wherein the ellipse comprises a short axis extending along a second direction and a ratio of the short axis to a diameter of the circle is greater than 0.7 and less than 1.3.

5. The semiconductor device of claim 4 , wherein the first direction is orthogonal to the second direction.

6. The semiconductor device of claim 1 , wherein a top view of the second metal interconnection comprises a quadrilateral.

7. The semiconductor device of claim 6 , wherein the first metal interconnection and the second metal interconnection are on a same level.

Priority Claims (1)
CN 201910384092.0 · May 9, 2019 · national
Continuity (4)
Continuation 17987795 · Nov 15, 2022
Continuation 17207728 · Mar 21, 2021
Continuation 16430437 · Jun 4, 2019
Related Publication 20240130140A1 · Apr 18, 2024
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