Semiconductor structure having air gap between gate electrode and distal end portion of active area and fabrication method thereof

1. A method for fabricating a semiconductor structure, comprising:

providing a semiconductor substrate having a major surface;

forming a trench isolation region and an active area surrounded by the trench isolation region in the semiconductor substrate, wherein the active area has a longitudinal axis extending along a first direction;

forming a first gate trench in the active area and a second gate trench in the trench isolation region;

forming a sacrificial spacer in the second gate trench;

forming a first gate electrode and a second gate electrode in the first gate trench and the second gate trench, respectively;

removing the sacrificial spacer from the second gate trench, thereby forming an air gap between the second gate electrode and the semiconductor substrate in the second gate trench, wherein the air gap overlaps with an entire thickness of the second gate electrode along a thickness direction that is perpendicular to a top surface of the semiconductor substrate; and

depositing a cap dielectric layer on the second gate electrode, wherein the cap dielectric layer seals the air gap, wherein the air gap is discontinuous along an extending direction of the second gate electrode under a top view.

2. The method according to claim 1 , wherein the sacrificial spacer is formed only in the second gate trench.

3. The method according to claim 2 , wherein the sacrificial spacer comprises silicon nitride.

4. The method according to claim 1 , wherein the sacrificial spacer covers a sidewall surface of a distal end portion of the active area between the first gate electrode and the second gate electrode.

5. The method according to claim 1 , wherein said forming the sacrificial spacer in the second gate trench comprises:

depositing a conformal spacer material layer on the semiconductor substrate, and in the first gate trench and the second gate trench;

selectively etching the spacer material layer, thereby forming a first spacer in the first gate trench and a second spacer in the second gate trench;

forming a planarization layer on the semiconductor substrate, and in the first gate trench and the second gate trench;

forming a photoresist pattern on the planarization layer;

etching the planarization layer, the first spacer, and the second spacer not covered by the photoresist pattern; and

removing remnants of the photoresist pattern and the planarization layer.

6. The method according to claim 1 , wherein the sacrificial spacer is removed by using a solution containing phosphoric acid or by using a soft etching process.

7. The method according to claim 6 , wherein the soft etching process comprises using remote plasma containing nitric oxide (NO) radicals and fluorine (F) radicals.

8. The method according to claim 1 , wherein the cap dielectric layer has a top surface that is flush with the major surface of the semiconductor substrate.

9. The method according to claim 1 , wherein the first gate trench and the second gate trench extend along a second direction that is not perpendicular to the first direction.