Interface circuit and packet transmission method thereof
A packet transmission method includes packaging a plurality of data in the form of a payload; storing information on whether the plurality of data are packaged in a header, the payload or a CRC area including a transmission error check code of the plurality of data; combining the header, the payload, and the CRC area with each other to generate a transaction layer packet; and outputting a packet including the transaction layer packet.
1. An interface circuit for transmitting and receiving first and second packets according to the Peripheral Component Interconnect Express (PCIe) protocol, the interface circuit comprising:
a reception circuit configured to receive the second packet; and
a transmission circuit configured to output the first packet, the transmission circuit including,
a payload generator configured to package a plurality of data into a payload of a transaction layer packet,
a header generator configured to generate a header of the transaction layer packet, the header including a bit indicating the plurality of data is packaged into the payload,
a combiner configured to generate the first packet from the transaction layer packet such that the first packet includes the payload, the header, and additional information, the additional information including at least a first CRC area and at least a pair of framing bits, the first CRC area including a transmission error check code of the plurality of data and the pair of framing bits indicating ends of the transaction layer packet within the first packet, and
a transmitter configured to output the first packet.
2. The interface circuit as set forth in claim 1 , wherein the header generator is configured to generate the header such that the header includes meta data to indicate addresses for the plurality of data.
3. The interface circuit as set forth in claim 1 , wherein the payload generator is configured to generate the payload such that the payload includes meta data to indicate addresses for the plurality of data.
4. The interface circuit as set forth in claim 1 , wherein the combiner is configured to generate a data link layer packet such that the data link layer packet includes a sequence number and a second CRC area at the ends of the transaction layer packet.
5. The interface circuit as set forth in claim 4 , wherein the combiner is configured to generate the first packet from the data link layer packet such that the first packet is a physical layer packet having the pair of framing bits that indicate the ends of the transaction layer packet added to both ends of the data link layer packet.
6. The interface circuit as set forth in claim 1 , wherein the reception circuit includes,
a receiver configured to receive the second packet; and
a decoder configured to determine whether the plurality of data is packaged into the second packet, and to decode a payload of the second packet to output the plurality of data.
7. The interface circuit as set forth in claim 6 , wherein the decoder is configured to determine whether the plurality of data is packaged by interpreting the second packet.
8. The interface circuit as set forth in claim 6 , wherein
the plurality of data is stored in a plurality of cache lines of a host processor, and
the interface circuit is configured to transmit the plurality of data after packaging the data into the first packet.