Forming vertical transistor devices with greater layout flexibility and packing density
A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.
1. A method of forming a fin field effect transistor circuit, comprising:
forming a plurality of vertical fins on a substrate;
forming a protective liner having a varying thickness on the substrate and plurality of vertical fins;
removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins and between at least one adjacent pair of the plurality of vertical fins;
removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas;
laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins; and
forming a first bottom source/drain layer in the widened trench.
2. The method of claim 1 , further comprising removing the first bottom source/drain layer from a widened trench, and forming a second bottom source/drain layer in the widened trench.
3. The method of claim 2 , wherein the first bottom source/drain layer includes a first dopant type, and the second bottom source/drain layer includes a second dopant type opposite the first dopant type.
4. The method of claim 3 further comprising heat treating the first bottom source/drain layer and second bottom source/drain layer to diffuse the first dopant type and the second dopant type into the supporting pillar to form an n-p junction.
5. The method of claim 4 , further comprising removing the protective liner segments from the plurality of vertical fins and from between the at least one adjacent pair of the plurality of vertical fins.
6. The method of claim 5 , further comprising forming a first gate structure on the plurality of vertical fins.
7. The method of claim 6 , further comprising forming top source/drains on the plurality of vertical fins.
8. The method of claim 7 , further comprising heat treating the top source/drains, first bottom source/drain layer, and second bottom source/drain layer, to form extension regions in the plurality of vertical fins.
9. The method of claim 8 , further comprising forming a bottom spacer layer between the first bottom source/drain layer and second bottom source/drain layer and the gate structure.