Page table entry caching for virtual device emulation

1. A method, comprising:

configuring, by a processing device executing a hypervisor, a page table entry in a host page table to map a guest address associated with memory-mapped input-output (MMIO) for a virtual device of a guest of the hypervisor to an input-output (I/O) instruction, wherein the I/O instruction is stored in the page table entry in lieu of a host address associated with the guest address;

setting, by the processing device executing the hypervisor, a reserve bit in the page table entry to mark the page table entry as a hypervisor exit entry, wherein marking the page table entry as the hypervisor exit entry causes the page table entry to signal to the processing device that the page table entry is valid and to be stored in a translation lookaside buffer (TLB) responsive to the guest attempting to access the guest address;

detecting, by the processing device executing the hypervisor, an exit to the hypervisor caused by the guest attempting to access the guest address in the page table entry marked as the hypervisor exit entry;

responsive to detecting the exit, receiving, by the processing device executing the hypervisor, the I/O instruction in the host page table, the received I/O instruction mapped to the guest address that caused the exit; and

executing, by the processing device executing the hypervisor, the I/O instruction on behalf of the guest.

2. The method of claim 1 , wherein configuring the page table entry comprises:

receiving the guest address associated with the MMIO and the I/O instruction from the guest; and

storing the guest address with the I/O instruction in the page table entry.

3. The method of claim 1 , wherein configuring the page table entry comprises:

identifying a physical device to be associated with the virtual device;

determining the guest address associated with the MMIO and the I/O instruction in view of attributes associated with the physical device;

storing the guest address with the I/O instruction in the page table entry; and

sending a notification to the guest with the guest address and the I/O instruction.

4. The method of claim 1 , wherein the page table entry is configured during initialization of the guest.

5. The method of claim 1 , wherein the page table entry is configured responsive to the guest attempting to access the guest address for a first time.

6. The method of claim 1 ,

wherein marking the page table entry indicates to the processing device that the guest writing to the guest address is to cause the exit.

7. The method of claim 6 , further comprising:

providing a notification that a value for the reserve bit indicates that the page table entry is to cause the exit.

8. A computing apparatus comprising:

a memory; and

a processing device, operatively coupled to the memory, to execute a hypervisor to:

configure a page table entry in a host page table to map a guest address associated with memory-mapped input-output (MMIO) for a virtual device of a guest of the hypervisor to an input-output (I/O) instruction, wherein the I/O instruction is stored in the page table entry in lieu of a host address associated with the guest address;

set a reserve bit in the page table entry to mark the page table entry as a hypervisor exit entry, wherein to mark the page table entry as the hypervisor exit entry causes the page table entry to signal to the processing device that the page table entry is valid and to be stored in a translation lookaside buffer (TLB) responsive to the guest attempting to access the guest address;

detect an exit to the hypervisor caused by the guest attempting to access the guest address in the page table entry marked as the hypervisor exit entry;

responsive to detecting the exit, receive the I/O instruction in the host page table, the received I/O instruction mapped to the guest address that caused the exit; and

execute the I/O instruction on behalf of the guest.

9. The computing apparatus of claim 8 , wherein the page table entry is stored in the TLB when the guest accesses the guest address.

10. The computing apparatus of claim 9 , wherein to configure the page table entry the processing device is to:

receive the guest address associated with the MMIO and the I/O instruction from the guest; and

store the guest address with the I/O instruction in the page table entry.

11. The computing apparatus of claim 9 , wherein to configure the page table entry the processing device is to:

identify a physical device to be associated with the virtual device;

determine the guest address associated with the MMIO and the I/O instruction in view of attributes associated with the physical device;

store the guest address with the I/O instruction in the page table entry; and

send a notification to the guest with the guest address and the I/O instruction.

12. The computing apparatus of claim 8 , wherein the page table entry is configured during initialization of the guest.

13. The computing apparatus of claim 8 , wherein the page table entry is configured responsive to the guest attempting to access the guest address for a first time.

14. The computing apparatus of claim 8 , wherein marking the page table entry indicates to the processing device that the guest writing to the guest address is to cause the exit.

15. The computing apparatus of claim 14 , wherein the processing device is further to notifying the processing device that a value for the reserve bit indicates that the page table entry is to cause the exit.

16. A non-transitory computer readable storage medium, having instructions stored therein, which when executed by a processing device of a computer system, cause the processing device to:

receive, by the processing device executing a hypervisor, a guest address associated with memory-mapped input-output (MMIO) for a virtual device of a guest of the hypervisor;

determine an input/output (I/O) instruction that corresponds with the guest address;

store an entry in a host page table to map the guest address to the I/O instruction; and

set a reserve bit in the entry to mark the entry in the host page table as a hypervisor exit entry, wherein marking the hypervisor exit entry is to cause an exit to the hypervisor and the page table entry to signal to the processing device that the page table entry is valid and to be stored in a translation lookaside buffer (TLB) responsive to the guest attempting to access the guest address.

17. The non-transitory computer readable storage medium of claim 16 , wherein marking the entry

indicates that the guest writing to the guest address is to cause the exit.

18. The non-transitory computer readable storage medium of claim 17 , wherein the processing device is further to:

provide a notification that a value for the reserve bit indicates that the page table entry is to cause the exit.

19. The non-transitory computer readable storage medium of claim 16 , wherein to receive the guest address, the processing device is to receive the guest address from the guest.