Three-dimensional (3D) tunneling field-effect transistor (FET)
A method for manufacturing a transistor device includes forming a plurality of fins on a substrate, performing an annealing process to cause the fins to have a round shape, growing an epitaxial semiconductor layer on a surface of each fin, wherein the epitaxial semiconductor layer is formed along the round shape, and forming a gate structure on the substrate, wherein the gate structure is formed on the epitaxial semiconductor layer on the surface of each fin.
1. A method for manufacturing a transistor device, comprising:
forming a plurality of fins on a substrate;
performing an annealing process to cause the fins to have a round shape;
growing an epitaxial semiconductor layer on a surface of each fin, wherein the epitaxial semiconductor layer is formed along the round shape;
forming a gate structure on the substrate, wherein the gate structure is formed on the epitaxial semiconductor layer on the surface of each fin;
laterally recessing a portion of a fin to form a vacant area under a corresponding epitaxial semiconductor layer on the fin;
wherein the vacant area leaves a portion of a bottom surface of the epitaxial semiconductor layer exposed;
filling the vacant area with a dielectric layer; and
growing an additional epitaxial semiconductor layer from an exposed lateral side of the corresponding epitaxial semiconductor layer on the fin.
2. The method according to claim 1 , wherein the annealing process is performed at a temperature in a range of about 500° C. to about 1200° C.
3. The method according to claim 2 , wherein the annealing process is performed in a hydrogen ambient.
4. The method according to claim 1 , wherein the round shape is at least one of circular and oval.
5. The method according to claim 1 , wherein each of the plurality of fins comprises a doped semiconductor material.
6. The method according to claim 5 , wherein each epitaxial semiconductor layer formed along the round shape comprises a semiconductor material different from the doped semiconductor material of the plurality of fins.
7. The method according to claim 5 , wherein each of the plurality of fins comprises a source/drain region of the transistor device.
8. The method according to claim 7 , wherein each epitaxial semiconductor layer comprises a channel region of the transistor device.
9. The method according to claim 1 , wherein the additional epitaxial semiconductor layer extends on to the substrate adjacent the dielectric layer.
10. The method according to claim 9 , wherein the fin comprises a semiconductor material having a first doping type, and the additional epitaxial semiconductor layer comprises a semiconductor material having a second doping type different from the first doping type.
11. The method according to claim 1 , wherein the transistor device comprises a tunnel field-effect transistor.
12. The method according to claim 1 , wherein the dielectric layer has a round shape.
13. The method according to claim 12 , wherein the epitaxial semiconductor layer is formed along the round shape of the dielectric layer.