Selectively regrown top contact for vertical semiconductor devices
Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
1. A semiconductor device, comprising:
a substrate having a surface;
a first source/drain region disposed on the surface of the substrate;
a first contact disposed on the first source/drain region, the first contact having a top surface;
a vertical channel region disposed on the first source/drain region and having a first width parallel with the surface of the substrate, and the vertical channel region having an upper portion and a lower portion;
a second source/drain region disposed on the vertical channel region and having a second width parallel with and substantially greater than the first width, wherein the second source/drain region is faceted with vertices located at a widest portion of the second source/drain region;
a second contact disposed on the second source/drain region, the second contact having a top surface above the top surface of the first contact; and
a gate stack comprising a gate dielectric and a gate electrode, the gate stack disposed on and completely surrounding the upper portion but not the lower portion of the vertical channel region, the gate dielectric of the gate stack further laterally surrounding a portion of the second source/drain region having a lateral width greater than a lateral width of the vertical channel region, wherein the second source/drain region extends above the gate stack.
2. The semiconductor device of claim 1 , wherein the first width is equal to or less than approximately 10 nanometers, and the second width is greater than 10 nanometers.
3. The semiconductor device of claim 1 , wherein the second source/drain region comprises a semiconductor material different from a semiconductor material of the vertical channel region.
4. The semiconductor device of claim 3 , wherein the semiconductor material of the second source/drain region is lattice mismatched from the semiconductor material of the vertical channel region, and wherein the second source/drain region imparts a strain to the vertical channel region.
5. The semiconductor device of claim 1 , further comprising:
a gate contact disposed on a horizontal extension of the gate stack.
6. The semiconductor device of claim 1 , wherein the first source/drain region is a drain region, and wherein the second source/drain region is a source region.
7. The semiconductor device of claim 1 , wherein the first source/drain region is a source region, and wherein the second source/drain region is a drain region.
8. The semiconductor device of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
9. The semiconductor device of claim 1 , wherein a conductivity type of the first source/drain region is the same as a conductivity type of the second source/drain region, and wherein the semiconductor device is a MOS-FET device.
10. The semiconductor device of claim 1 , wherein a conductivity type of the first source/drain region is opposite to a conductivity type of the second source/drain region, and wherein the semiconductor device is a tunnel FET device.
11. A semiconductor device, comprising:
a substrate having a surface;
a first source/drain region disposed on the surface of the substrate;
a first contact disposed on the first source/drain region, the first contact having a top surface;
a vertical channel region disposed on the first source/drain region and comprising a semiconductor material, and the vertical channel region having an upper portion and a lower portion;
a second source/drain region disposed on the vertical channel region, wherein the second source/drain region comprises a semiconductor material different from and lattice mismatched with the semiconductor material of the vertical channel region, wherein the second source/drain region is faceted with vertices located at a widest portion of the second source/drain region;
a second contact disposed on the second source/drain region, the second contact having a top surface above the top surface of the first contact; and
a gate stack comprising a gate dielectric and a gate electrode, the gate stack disposed on and completely surrounding the upper portion but not the lower portion of the vertical channel region, the gate dielectric of the gate stack further laterally surrounding a portion of the second source/drain region having a lateral width greater than a lateral width of the vertical channel region, wherein the second source/drain region extends above the gate stack.
12. The semiconductor device of claim 11 , wherein the second source/drain region imparts a strain to the vertical channel region.
13. The semiconductor device of claim 11 , further comprising:
a gate contact disposed on a horizontal extension of the gate stack.
14. The semiconductor device of claim 11 , wherein the first source/drain region is a drain region, and wherein the second source/drain region is a source region.
15. The semiconductor device of claim 11 , wherein the first source/drain region is a source region, and wherein the second source/drain region is a drain region.
16. The semiconductor device of claim 11 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
17. The semiconductor device of claim 11 , wherein a conductivity type of the first source/drain region is the same as a conductivity type of the second source/drain region, and wherein the semiconductor device is a MOS-FET device.
18. The semiconductor device of claim 11 , wherein a conductivity type of the first source/drain region is opposite to a conductivity type of the second source/drain region, and wherein the semiconductor device is a tunnel FET device.
19. A method of fabricating a semiconductor device, the method comprising:
forming a first source/drain region on the surface of a substrate;
forming, from a first semiconductor material, a vertical channel region on the first source/drain region and having a first width parallel with the surface of the substrate, and the vertical channel region having an upper portion and a lower portion;
forming, from a second semiconductor material, a second source/drain region on the vertical channel region and having a second width parallel with and substantially greater than the first width, wherein the second source/drain region is faceted with vertices located at a widest portion of the second source/drain region;
forming a gate stack comprising a gate dielectric and a gate electrode, the gate stack on and completely surrounding the upper portion but not the lower portion of the vertical channel region, the gate dielectric of the gate stack further laterally surrounding a portion of the second source/drain region having a lateral width greater than a lateral width of the vertical channel region, wherein the second source/drain region extends above the gate stack,
forming a first contact on the first source/drain region, the first contact having a top surface; and
forming a second contact on the second source/drain region, the second contact having a top surface above the top surface of the first contact.
20. The method of claim 19 , wherein forming the second source/drain region on the vertical channel region comprises epitaxially growing the second semiconductor material on the first semiconductor material.
21. The method of claim 20 , wherein epitaxially growing the second semiconductor material on the first semiconductor material comprises epitaxially growing the second semiconductor material lattice mismatched with the first semiconductor material.
22. The method of claim 19 , wherein forming the first source/drain region comprises forming a drain region, and wherein forming the second source/drain region comprises forming a source region.
23. The method of claim 19 , wherein forming the first source/drain region comprises forming a source region, and wherein forming the second source/drain region comprises forming a drain region.