Controlling the number of powered vector lanes via a register field
The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2 VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.
1. A digital data processor comprising:
a register having a vector lane number field to store a vector lane number, wherein the vector lane number field includes a plurality of bits;
a vector data path having a plurality of vectors lanes, wherein each of the vectors lanes is configured to be separately and selectively powered, and wherein the number of bits of the vector lane number field is less than the number of vector lanes of the vector data path;
a decoder coupled to the register and to the vector data path, wherein the decoder is configured to receive the vector lane number from the register and to determine a vector lane control word corresponding to the vector lane number, wherein the vector lane control word includes a plurality of bits, the number of bits of the vector lane control word is equal to the number of vector lanes of the vector data path, the number of bits of the vector lane control word is greater than the number of bits decoded by the decoder to determine the vector lane control word, and each bit of the vector lane control word corresponds to a respective one of the vector lanes, wherein a number of vector lanes required is not an integer power of two and the decoder is configured to utilize a next higher integer power of two number of vector lanes; and
control logic configured to control the powering of each of the vector lanes in response to the vector lane control word, wherein, for each vector lane, the vector lane is controlled to be power on if the bit of the vector lane control word corresponding to the vector lane has a first value and is controlled to be powered off if the bit of the vector lane control word corresponding to the vector lane has a second value.
2. The digital data processor of claim 1 , wherein the vector lane number is a binary value represented by the number of bits of the vector lane number field, wherein each of a plurality of possible binary values that can be represented by the vector lane number corresponds to a respective decimal value M, and wherein the vector lane control word corresponding to the vector lane number causes 2 M vector lanes to be powered on.
3. The digital data processor of claim 2 , wherein the 2 M vector lanes are contiguous vector lanes of the vector data path.
4. The digital data processor of claim 3 , wherein the contiguous vector lanes are a contiguous group of least significant vector lanes of the plurality of vector lanes when 2 M is less than the number of vector lanes, and are all the vector lanes of the plurality of vector lanes when 2 M is equal to the number of vector lanes.
5. The digital data processor of claim 4 , wherein the decoder includes a look-up table having a plurality of entries that include all possible vector lane control words indexed by a corresponding vector lane number.
6. The digital data processor of claim 5 , wherein:
the vector lane number field consists of 3 bits;
the plurality of vector lanes includes 32 vector lanes; and
the plurality of entries of the look-up table includes:
Vector Lane
Number
Vector Lane Control Word
000
0000
0000
0000
0000
0000
0000
0000
0001
001
0000
0000
0000
0000
0000
0000
0000
0011
010
0000
0000
0000
0000
0000
0000
0000
1111
011
0000
0000
0000
0000
0000
0000
1111
1111
100
0000
0000
0000
0000
1111
1111
1111
1111
101
1111
1111
1111
1111
1111
1111
1111
1111.
7. The digital data processor of claim 6 , wherein the vector data path is 256 bits wide, and wherein each vector lane is 8 bits.
8. The digital data processor of claim 1 , wherein all vector lanes powered on by the control logic are contiguous vector lanes within the vector data path.
9. The digital data processor of claim 1 , wherein the first value is a logical 1 and the second value is a logical 0.
10. The digital data processor of claim 1 , wherein each possible vector lane number corresponds to a unique vector lane control word.
11. The digital data processor of claim 1 , comprising:
a first execution unit;
a second execution unit; and
a register file, wherein register file is coupled to each of the first execution unit and the second execution unit by the vector data path, and wherein the vector data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the vector data path, reading from the register file by the first execution unit is allowed over the vector data path, and reading from the register file by the second execution unit is not allowed over the vector data path.