Integrated circuit and method of manufacturing same
An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
1. A method of forming an integrated circuit, the method comprising:
generating, by a processor, a layout design of the integrated circuit, wherein generating the layout design comprises:
generating a set of active region layout patterns extending in a first direction, being located on a first layout level, and being separated from one another in a second direction different from the first direction, the set of active region layout patterns corresponding to fabricating a set of active regions within a substrate of the integrated circuit;
generating a first set of conductive feature layout patterns extending in at least the first direction or the second direction, being located on the first layout level, and being between the set of active region layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures of the integrated circuit within the substrate;
generating a set of gate layout patterns extending in the second direction, overlapping at least the first set of conductive feature layout patterns and being located on a second layout level different from the first layout level, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, the set of gate layout patterns corresponding to fabricating a set of gates of the integrated circuit;
generating a set of metal over diffusion layout patterns corresponding to fabricating a set of contacts of the integrated circuit, the set of metal over diffusion layout patterns extending in the second direction, overlapping the first set of conductive feature layout patterns, and being located on the second layout level, each of the layout patterns of the set of metal over diffusion patterns being separated from an adjacent layout pattern of the set of metal over diffusion layout patterns in the first direction; and
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling the first set of conductive structures to the set of contacts, the first set of via layout patterns being between the first set of conductive feature layout patterns and the set of metal over diffusion layout patterns, and a layout pattern of the first set of via layout patterns being located where a layout pattern of the set of metal over diffusion layout patterns overlaps a layout pattern of the first set of conductive feature layout patterns; and
manufacturing the integrated circuit based on the layout design.
2. The method of claim 1 , wherein generating the layout design further comprises:
generating a second set of conductive feature layout patterns corresponding to fabricating a second set of conductive structures of the integrated circuit, the second set of conductive feature layout patterns extending in the first direction, being between the set of active region layout patterns, overlapping at least the set of gate layout patterns, and being located on a third layout level different from the first layout level and the second layout level, and each of the layout patterns of the second set of conductive feature layout patterns being separated from an adjacent layout pattern of the second set of conductive feature layout patterns in the second direction.
3. The method of claim 2 , wherein generating the layout design further comprises:
generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias coupling the second set of conductive structures to the set of gates, the second set of via layout patterns being between the second set of conductive feature layout patterns and the set of gate layout patterns, and a layout pattern of the second set of via layout patterns being located where a layout pattern of the second set of conductive feature layout patterns overlaps a layout pattern of the set of gate layout patterns.
4. The method of claim 3 , wherein generating the layout design further comprises:
generating a third set of conductive feature layout patterns corresponding to fabricating a third set of conductive structures of the integrated circuit, the third set of conductive feature layout patterns extending in the second direction, being between the set of gate layout patterns, overlapping at least the first set of conductive feature layout patterns, and being located on a fourth layout level different from the first layout level, the second layout level and the third layout level, and each of the layout patterns of the third set of conductive feature layout patterns being separated from an adjacent layout pattern of the third set of conductive feature layout patterns in the first direction; and
generating a fourth set of via layout patterns corresponding to fabricating a fourth set of vias, the fourth set of vias coupling the third set of conductive structures to the second set of conductive structures, the fourth set of via layout patterns being between the third set of conductive feature layout patterns and the second set of conductive feature layout patterns, and a layout pattern of the fourth set of via layout patterns being located where a layout pattern of the third set of conductive feature layout patterns overlaps another layout pattern of the second set of conductive feature layout patterns.
5. The method of claim 1 , wherein generating the layout design further comprises:
generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias coupling the first set of conductive structures to the set of gates, the second set of via layout patterns being between the first set of conductive feature layout patterns and the set of gate layout patterns, and a layout pattern of the second set of via layout patterns being located where a layout pattern of the set of gate layout patterns overlaps the layout pattern of the first set of conductive feature layout patterns.
6. The method of claim 1 , wherein generating the layout design further comprises:
generating a set of fin layout patterns corresponding to fabricating a set of fins of the integrated circuit, the set of fin layout patterns extending in the first direction and below the set of gate layout patterns, each of the layout patterns of the set of fin layout patterns being separated from an adjacent layout pattern of the set of fin layout patterns in the second direction by a fin pitch.
7. The method of claim 1 , wherein generating the layout design further comprises:
generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gates of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns.
8. The method of claim 7 , further comprising:
removing a portion of the first gate of the set of gates to form a first gate structure and a second gate structure, and the cut feature layout pattern identifying a location of the removed portion of the first gate of the set of gates.
9. A method of forming an integrated circuit, the method comprising:
generating, by a processor, a layout design of the integrated circuit, wherein generating the layout design comprises:
placing a set of active region layout patterns on a first layout level, the set of active region layout patterns extending in a first direction, and being separated from one another in a second direction different from the first direction, the set of active region layout patterns corresponding to fabricating a set of active regions within a substrate of the integrated circuit;
placing a first set of conductive feature layout patterns on the first layout level, the first set of conductive feature layout patterns extending in at least the first direction or the second direction, and being between the set of active region layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures within the substrate of the integrated circuit;
placing a set of metal over diffusion layout patterns on a second layout level different from the first layout level, the set of metal over diffusion layout patterns corresponding to fabricating a set of contacts of the integrated circuit, the set of contacts being electrically coupled to the set of active regions of the integrated circuit, the set of metal over diffusion layout patterns extending in the second direction, and overlapping the first set of conductive feature layout patterns, each of the layout patterns of the set of metal over diffusion layout patterns being separated from an adjacent layout pattern of the set of metal over diffusion layout patterns in the first direction; and
placing a first set of via layout patterns between the first set of conductive feature layout patterns and the set of metal over diffusion layout patterns, the first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling the first set of conductive structures to the set of contacts, and a layout pattern of the first set of via layout patterns being located where a layout pattern of the set of metal over diffusion layout patterns overlaps a layout pattern of the first set of conductive feature layout patterns; and
manufacturing the integrated circuit based on the layout design, the integrated circuit comprising a transmission gate.
10. The method of claim 9 , wherein generating the layout design further comprises:
placing a second set of conductive feature layout patterns on a third layout level different from the first layout level and the second layout level, the second set of conductive feature layout patterns corresponding to fabricating a second set of conductive structures of the integrated circuit, the second set of conductive feature layout patterns extending in the first direction, being between the set of active region layout patterns, and overlapping at least the first set of conductive feature layout patterns, and each of the layout patterns of the second set of conductive feature layout patterns being separated from an adjacent layout pattern of the second set of conductive feature layout patterns in the second direction; and
placing a second set of via layout patterns between the second set of conductive feature layout patterns and the set of metal over diffusion layout patterns, the second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias coupling the second set of conductive structures to the set of contacts, and a layout pattern of the second set of via layout patterns being located where a layout pattern of the second set of conductive feature layout patterns overlaps another layout pattern of the set of metal over diffusion layout patterns.
11. The method of claim 9 , wherein generating the layout design further comprises:
placing a set of gate layout patterns on the second layout level, the set of gate layout patterns extending in the second direction, and overlapping at least the first set of conductive feature layout patterns, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, and the set of gate layout patterns corresponding to fabricating a set of gates of the integrated circuit.
12. The method of claim 11 , wherein generating the layout design further comprises:
placing a second set of via layout patterns between the first set of conductive feature layout patterns and the set of gate layout patterns, the second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias coupling the first set of conductive structures to the set of gates, and a layout pattern of the second set of via layout patterns being located where a layout pattern of the set of gate layout patterns overlaps the layout pattern of the first set of conductive feature layout patterns.
13. A method of forming an integrated circuit, the method comprising:
generating, by a processor, a layout design of the integrated circuit, wherein generating the layout design comprises:
generating a set of active region layout patterns extending in a first direction, being located on a first layout level, and being separated from one another in a second direction different from the first direction, the set of active region layout patterns corresponding to fabricating a set of active regions within a substrate of the integrated circuit;
generating a first conductive feature layout pattern extending in the first direction, being located on the first layout level, and being between the set of active region layout patterns, the first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit within the substrate;
generating a set of gate layout patterns extending in the second direction, overlapping at least the first conductive feature layout pattern and being located on a second layout level different from the first layout level, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, the set of gate layout patterns corresponding to fabricating a set of gates of the integrated circuit; and
generating a set of metal over diffusion layout patterns corresponding to fabricating a set of contacts of the integrated circuit, the set of metal over diffusion layout patterns extending in the second direction, overlapping the first conductive feature layout pattern, and being located on the second layout level, each of the layout patterns of the set of metal over diffusion patterns being separated from an adjacent layout pattern of the set of metal over diffusion layout patterns in the first direction; and
manufacturing the integrated circuit based on the layout design.
14. The method of claim 13 , wherein generating the layout design further comprises:
generating a second conductive feature layout pattern extending in the first direction, being located on the first layout level, being between the set of active region layout patterns, and being separated from the first conductive feature layout pattern in the second direction, and the second conductive feature layout pattern corresponding to fabricating a second conductive structure of the integrated circuit within the substrate.
15. The method of claim 14 , wherein generating the layout design further comprises:
generating a third conductive feature layout pattern extending in the second direction, being located on the first layout level, being between the set of active region layout patterns, contacting the first conductive feature layout pattern and the second conductive feature layout pattern, and the third conductive feature layout pattern corresponding to fabricating a third conductive structure of the integrated circuit within the substrate.
16. The method of claim 14 , wherein generating the layout design further comprises:
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling at least the first conductive structure or the second conductive structure to the set of gates, the first set of via layout patterns being between at least the first conductive feature layout pattern or the second conductive feature layout pattern and the set of gate layout patterns, and a layout pattern of the first set of via layout patterns being located where a layout pattern of the set of gate layout patterns overlaps at least the first conductive feature layout pattern or the second conductive feature layout pattern.
17. The method of claim 14 , wherein generating the layout design further comprises:
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling at least the first conductive structure or the second conductive structure to the set of contacts, the first set of via layout patterns being between at least the first conductive feature layout pattern or the second conductive feature layout pattern and the set of metal over diffusion layout patterns, and a layout pattern of the first set of via layout patterns being located where a layout pattern of the set of metal over diffusion layout patterns overlaps at least the first conductive feature layout pattern or the second conductive feature layout pattern.
18. The method of claim 13 , wherein generating the layout design further comprises:
generating a first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures of the integrated circuit, the first set of conductive feature layout patterns extending in the first direction, being between the set of active region layout patterns, overlapping at least the set of gate layout patterns, and being located on a third layout level different from the first layout level and the second layout level, and each of the layout patterns of the first set of conductive feature layout patterns being separated from an adjacent layout pattern of the first set of conductive feature layout patterns in the second direction; and
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling the first set of conductive structures to the set of gates, the first set of via layout patterns being between the first set of conductive feature layout patterns and the set of gate layout patterns, and at least a layout pattern of the first set of via layout patterns being located where the first set of conductive feature layout patterns overlaps a layout pattern of the set of gate layout patterns.
19. The method of claim 18 , wherein generating the layout design further comprises:
generating a second set of conductive feature layout patterns corresponding to fabricating a second set of conductive structures of the integrated circuit, the second set of conductive feature layout patterns extending in the second direction, being between the set of gate layout patterns, overlapping at least the first set of conductive feature layout patterns, and being located on a fourth layout level different from the first layout level, the second layout level and the third layout level, and each of the layout patterns of the second set of conductive feature layout patterns being separated from an adjacent layout pattern of the second set of conductive feature layout patterns in the first direction; and
generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias coupling the first set of conductive structures to the second set of conductive structures, the second set of via layout patterns being between the first set of conductive feature layout patterns and the second set of conductive feature layout patterns, and a layout pattern of the second set of via layout patterns being located where the second set of conductive feature layout patterns overlaps a layout pattern of the first set of conductive feature layout patterns.
20. The method of claim 13 , wherein generating the layout design further comprises:
generating a set of fin layout patterns corresponding to fabricating a set of fins of the integrated circuit, the set of fin layout patterns extending in the first direction and being below the set of gate layout patterns, each of the layout patterns of the set of fin layout patterns being separated from an adjacent layout pattern of the set of fin layout patterns in the second direction by a fin pitch.