IP Library › Granted Patent US 10,734,403
Granted Patent B2
US 10,734,403 · App. 15/991,309 · Granted Aug 4, 2020

Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same

Inventors: Taeyong Eom (Anyang-si, KR); Jiwoon Im (Hwaseong-si, KR); Byungsun Park (Suwon-si, KR); Hyunseok Lim (Suwon-si, KR); Yu Seon Kang (Hwaseong-si, KR); Hyukho Kwon (Hwaseong-si, KR); Sungjin Park (Seongnam-si, KR); Jiyoun Seo (Seoul, KR); Dong Hyeop Ha (Daegu, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L27/11582G11C16/02H01L27/1157H01L27/11543
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Quick Facts
Patent No.
US 10,734,403
App. No.
15/991,309
Granted
Aug 4, 2020
Kind
B2
Abstract

Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

Claims (53)

1. A nonvolatile memory device comprising:

a stacked structure comprising a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate; and

a vertical channel structure extending through the stacked structure, wherein the plurality of conductive films comprise a selection line that is closest to the substrate among the plurality of conductive films,

wherein the selection line comprises a lower portion and an upper portion sequentially stacked on the substrate,

wherein a side of the upper portion of the selection line and a side of the lower portion of the selection line have different profiles, and

wherein the vertical channel structure comprises:

a dielectric film on a sidewall of the stacked structure;

a channel film on the dielectric film, the channel film defining a space therein; and

a filling film on the channel film, the filling film filling the space defined by the channel film,

wherein a lower surface of the filling film is closer to an upper surface of the substrate than a lower surface of the selection line.

2. The nonvolatile memory device of claim 1 , wherein the filling film extends on the upper surface of the substrate.

3. The nonvolatile memory device of claim 1 , wherein the selection line directly contacts the channel film.

4. The nonvolatile memory device of claim 1 , wherein the side of the lower portion of the selection line has a first angle with respect to the upper surface of the substrate, and the side of the upper portion of the selection line has a second angle with respect to the upper surface of the substrate, and

wherein the first angle is greater than the second angle.

5. The nonvolatile memory device of claim 1 , wherein the vertical channel structure comprises a first recess contacting the lower portion of the selection line, and

a second recess contacting the upper portion of the selection line, and

wherein a first depth of the first recess is different from a second depth of the second recess.

6. The nonvolatile memory device of claim 5 , wherein the lower portion of the selection line fills the first recess, and the upper portion of the selection line fills the second recess.

7. The nonvolatile memory device of claim 5 , wherein the first depth of the first recess is greater than the second depth of the second recess.

8. The nonvolatile memory device of claim 5 , wherein the vertical channel structure comprises a protrusion between the first recess and the second recess.

9. The nonvolatile memory device of claim 5 , wherein the selection line comprises a concave portion between the upper portion and the lower portion of the selection line.

10. The nonvolatile memory device of claim 1 , wherein a lower surface of the vertical channel structure directly contacts the upper surface of the substrate.

11. A nonvolatile memory device comprising:

a stacked structure comprising a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate; and

a vertical channel structure extending through the stacked structure,

wherein the plurality of conductive films comprise a first conductive film that is closest to the substrate among the plurality of conductive films,

wherein the first conductive film comprises a lower portion and an upper portion sequentially stacked on the substrate,

wherein a side of the upper portion of the first conductive film has a profile different from a profile of a side of the lower portion of the first conductive film, and

wherein the vertical channel structure comprises:

a dielectric film on a sidewall of the stacked structure;

a channel film on the dielectric film, the channel film defining a space therein; and

a filling film on the channel film, the filling film filling the space defined by the channel film,

wherein a lower surface of the filling film is closer to an upper surface of the substrate than a lower surface of the first conductive film.

12. The nonvolatile memory device of claim 11 , wherein the vertical channel structure comprises a first recess contacting the lower portion of the first conductive film, and a second recess contacting the upper portion of the first conductive film, and

wherein a first depth of the first recess is different from a second depth of the second recess.

13. The nonvolatile memory device of claim 12 , wherein the first depth of the first recess is greater than the second depth of the second recess.

14. The nonvolatile memory device of claim 12 , wherein the vertical channel structure comprises a protrusion between the first recess and the second recess.

15. The nonvolatile memory device of claim 11 , wherein the plurality of conductive films further comprise a second conductive film, and

wherein the first conductive film has a first thickness in a vertical direction, the second conductive film has a second thickness in the vertical direction, and the first thickness is greater than the second thickness.

16. A nonvolatile memory device comprising:

a stacked structure comprising a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate; and

a vertical channel structure extending through the stacked structure,

wherein the plurality of conductive films comprise a selection line that is closest to the substrate among the plurality of conductive films,

wherein the selection line comprises a lower portion and an upper portion sequentially stacked on the substrate,

wherein a side of the lower portion of the selection line has a first angle with respect to an upper surface of the substrate, and a side of the upper portion of the selection line has a second angle with respect to the upper surface of the substrate, and

wherein the first angle is greater than the second angle.

17. The nonvolatile memory device of claim 16 , wherein the vertical channel structure comprises:

a dielectric film on a sidewall of the stacked structure;

a channel film on the dielectric film, the channel film defining a space therein; and

a filling film in the space defined by the channel film.

18. The nonvolatile memory device of claim 17 , wherein the filling film directly contacts the upper surface of the substrate.

19. The nonvolatile memory device of claim 18 , wherein the selection line directly contacts the channel film.

20. The nonvolatile memory device of claim 16 , wherein a lower surface of the vertical channel structure directly contacts the upper surface of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2018
From: EOM, TAEYONG; IM, JIWOON; PARK, BYUNGSUN; LIM, HYUNSEOK; KANG, YU SEON; KWON, HYUKHO; PARK, SUNGJIN; SEO, JIYOUN; HA, DONG HYEOP
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 045922/0788 →
Priority Claims (1)
KR 10-2017-0115384 · Sep 8, 2017 · national
Continuity (2)
Related Publication 20190081067A1 · Mar 14, 2019
Related Publication 20200194449A9 · Jun 18, 2020
Cited By (1)
US 12,274,056