Semiconductor devices including ferroelectric layer and methods of fabricating the same

1. A method of fabricating a semiconductor device, the method comprising:

forming a stack layer structure including a plurality of interlayer insulation layers and a plurality of interlayer sacrificial layers alternately stacked on a substrate;

forming a trench that penetrates the stack layer structure on the substrate;

forming a capping oxide layer on a sidewall of the trench;

forming a ferroelectric insulation layer on the capping oxide layer and a channel layer on the ferroelectric insulation layer;

selectively removing the plurality of interlayer sacrificial layers and portions of the capping oxide layer to form recesses that expose portions of the ferroelectric insulation layer; and

filling the recesses with a conductive layer to form gate electrode layers in the recesses.

2. The method of claim 1 , wherein the capping oxide layer has a lattice constant which is different from a lattice constant of the ferroelectric insulation layer.

3. The method of claim 1 , wherein an oxygen vacancy concentration of the capping oxide layer is higher than an oxygen vacancy concentration of the ferroelectric insulation layer.

4. The method of claim 1 ,

wherein the capping oxide layer and the ferroelectric insulation layer are formed to include the same metal oxide material; and

wherein the capping oxide layer includes dopants distributed therein.

5. The method of claim 4 , wherein the metal oxide material includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

6. The method of claim 4 ,

wherein the dopants distributed in the capping oxide layer include at least one selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La) and zirconium (Zr).

7. The method of claim 1 , wherein forming the ferroelectric insulation layer and the channel layer includes

forming a ferroelectric material having an amorphous phase on the capping oxide layer;

forming a semiconductor material on the ferroelectric material; and

annealing the ferroelectric material to crystallize the ferroelectric material to form the ferroelectric insulation layer.

8. The method of claim 1 , wherein selectively removing the plurality of interlayer sacrificial layers and portions of the capping oxide layer includes

selectively removing the plurality of interlayer sacrificial layers with a wet etch technique to expose portions of the capping oxide layer; and

selectively removing the exposed portions of the capping oxide layer with a wet etch technique to expose portions of the ferroelectric insulation layer.

9. A method of fabricating a semiconductor device, the method comprising:

forming a capping oxide layer on a substrate;

sequentially forming a ferroelectric material having an amorphous phase and a channel layer on the capping oxide layer;

annealing the ferroelectric material to form a ferroelectric insulation layer having a crystalline structure; and

forming a gate electrode layer in contact with at least a portion of the ferroelectric insulation layer,

wherein the capping oxide layer has a lattice constant which is different from a lattice constant of the ferroelectric insulation layer, and

wherein an oxygen vacancy concentration of the capping oxide layer is higher than an oxygen vacancy concentration of the ferroelectric insulation layer.

10. The method of claim 9 ,

wherein the capping oxide layer and the ferroelectric insulation layer are formed to include the same metal oxide material; and

wherein the metal oxide material includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

11. The method of claim 9 ,

wherein the capping oxide layer includes dopants distributed therein; and

wherein the dopants distributed in the capping oxide layer include at least one selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La) and zirconium (Zr).

12. The method of claim 9 , wherein forming the gate electrode layer includes

etching at least a portion of the capping oxide layer to form a recess exposing a portion of the ferroelectric insulation layer; and

filling the recess with a conductive layer.