MOS devices having epitaxy regions with reduced facets
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
1. A semiconductor device comprising:
a gate structure at a top surface of a semiconductor substrate;
a source/drain region adjacent the gate structure, the source/drain region comprising:
a first germanium comprising region;
a silicon germanium cap over the first germanium comprising region and above the semiconductor substrate, the silicon germanium cap having a lower germanium percentage than the first germanium comprising region; and
a silicide extending through the silicon germanium cap, wherein the silicide has a higher germanium percentage than the silicon germanium cap, and at least a portion of the silicide has a higher germanium percentage than a silicon percentage.
2. The semiconductor device of claim 1 further comprising a second germanium comprising region under the first germanium comprising region, wherein the second germanium comprising region has a lower germanium concentration than the first germanium comprising region.
3. The semiconductor device of claim 2 , wherein the first germanium comprising region contacts the silicon germanium cap, and wherein a portion of the first germanium comprising region in contact with the silicon germanium cap has a highest germanium percentage among the first and the second germanium comprising regions.
4. The semiconductor device of claim 1 further comprising, wherein the silicide extends into the first germanium comprising region.
5. The semiconductor device of claim 1 further comprising a contact contacting a top of the silicide, wherein a portion of the silicon germanium cap is between a side of the silicide and the contact.
6. The semiconductor device of claim 1 further comprising a p-type impurity in the silicon germanium cap.
7. The semiconductor device of claim 1 , wherein the silicon germanium cap comprises less than 2% germanium.
8. A PMOS transistor comprising:
a gate stack at a top surface of a semiconductor substrate; and
a source/drain region, the source/drain region comprising:
a lower portion having a first germanium percentage; and
an upper portion over the lower portion of the source/drain region and having a second germanium percentage greater than the first germanium percentage;
a capping layer over the source/drain region, wherein the capping layer has a third germanium percentage lower than the second germanium percentage; and
a silicide spanning across a boundary between the capping layer and the source/drain region, wherein the silicide has a fourth germanium percentage greater than the third germanium percentage.
9. The PMOS transistor of claim 8 , wherein a germanium percentage of the source/drain region gradually increases in a direction from the lower portion to the upper portion.
10. The PMOS transistor of claim 8 , wherein the second germanium percentage is at least 45 percent.
11. The PMOS transistor of claim 8 , wherein the third germanium percentage is lower than the first germanium percentage.
12. The PMOS transistor of claim 8 , wherein a germanium percentage of the silicide is greater than a silicon percentage of the silicide.
13. The PMOS transistor of claim 8 , wherein the silicide extends through the capping layer.
14. The PMOS transistor of claim 8 further comprising a p-type impurity in the capping layer, wherein a p-type impurity concentration in the capping layer is higher than a p-type impurity concentration in upper portion of the source/drain region or the lower portion of the source/drain region.
15. A semiconductor device comprising:
a semiconductor substrate;
a gate stack on the semiconductor substrate;
an epitaxial region adjacent the gate stack;
a capping layer over the epitaxial region;
a silicide extending from a top surface of the capping layer into the epitaxial region, the silicide having a higher concentration of germanium than the capping layer;
a dielectric layer over the capping layer and around the gate stack; and
a contact electrically connected to the silicide, wherein the silicide extends along and is physically separated from a side surface of the contact.
16. The semiconductor device of claim 15 , wherein the capping layer has a lower germanium percentage than the epitaxial region.
17. The semiconductor device of claim 16 , wherein the capping layer is free of germanium.
18. The semiconductor device of claim 15 , wherein the capping layer comprises silicon germanium.
19. The semiconductor device of claim 15 , wherein the epitaxial region and the capping layer each comprise p-type impurities.
20. The semiconductor device of claim 15 , wherein a germanium concentration of the silicide is greater than a silicon concentration of the silicide.