Memory device and fabrication method thereof
A memory device includes an inter-layer dielectric (ILD) layer, a metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a bottom electrode via. The metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer. The memory cell is over the metal-containing compound layer and includes a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The bottom electrode via connects the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.
1. A memory device, comprising:
an inter-layer dielectric (ILD) layer;
a metallization pattern in the ILD layer;
an etch stop layer over the ILD layer;
a metal-containing compound layer over the etch stop layer;
a memory cell over the metal-containing compound layer and comprising a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; and
a bottom electrode via connecting the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.
2. The memory device of claim 1 , wherein a top surface of the bottom electrode via is higher than a top surface of the metal-containing compound layer.
3. The memory device of claim 1 , further comprising:
a memory dielectric layer has a first portion extending along a top surface of the metal-containing compound layer and a second portion extending upwardly along sidewalls of the bottom electrode via.
4. The memory device of claim 3 , wherein a top surface of the bottom electrode via is substantially coplanar with a top surface of the second portion of the memory dielectric layer.
5. The memory device of claim 3 , wherein the bottom electrode is in contact with a top surface of the second portion of the memory dielectric layer.
6. The memory device of claim 3 , further comprising:
a spacer extending along sidewalls of the memory cell, wherein a bottom surface of the spacer is in contact with a top surface of the first portion of the memory dielectric layer.
7. The memory device of claim 1 , wherein the metal-containing compound layer comprises an aluminum-based dielectric material.
8. The memory device of claim 1 , wherein the metal-containing compound layer is in contact with the etch stop layer.
9. A memory device, comprising:
a memory region and a logic region adjacent to the memory region;
a first inter-layer dielectric (ILD) layer;
a metallization pattern in the first ILD layer;
a metal-containing compound layer over the first ILD layer and within the memory region, wherein the logic region is free of the metal-containing compound layer; and
a memory cell over the metal-containing compound layer, within the memory region, and comprising a bottom electrode, a resistance switching element over the bottom electrode and a top electrode over the resistance switching element.
10. The memory device of claim 9 , further comprising:
a bottom electrode via connecting the bottom electrode to the metallization pattern, wherein the bottom electrode via is surrounded by the metal-containing compound layer.
11. The memory device of claim 10 , further comprising:
a memory dielectric layer within the memory region and over the metal-containing compound layer, wherein the bottom electrode via is surrounded by the memory dielectric layer.
12. The memory device of claim 11 , wherein the logic region is free of the memory dielectric layer.
13. The memory device of claim 9 , further comprising:
an etch stop layer over the first ILD layer and comprising a first portion within the memory region and a second portion within the logic region.
14. The memory device of claim 13 , wherein the first portion of the etch stop layer is between the metal-containing compound layer and the first ILD layer.
15. The memory device of claim 13 , further comprising:
a second ILD layer over and in contact with the second portion of the etch stop layer.
16. A semiconductor device, comprising:
an inter-layer dielectric (ILD) layer;
a conductive feature in the ILD layer;
a bottom electrode via connected to the conductive feature;
a memory cell over the bottom electrode via, wherein the memory cell comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element;
a metal-containing compound layer surrounding the bottom electrode via; and
a memory dielectric layer interposed between the bottom electrode of the memory cell and the metal-containing compound layer.
17. The semiconductor device of claim 16 , further comprising:
a dielectric layer interposed between the conductive feature and the metal-containing compound layer.
18. The semiconductor device of claim 17 , wherein the dielectric layer extends beyond a bottom surface of the metal-containing compound layer.
19. The semiconductor device of claim 16 , further comprising:
a spacer on a sidewall of the memory cell and a sidewall of the memory dielectric layer.
20. The semiconductor device of claim 16 , wherein the memory cell is directly above the bottom electrode via.